2011-07-20 22:36:56 -06:00
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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2012-05-11 08:24:17 -06:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2011-07-20 22:36:56 -06:00
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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2013-07-01 02:16:10 -06:00
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#include <linux/clk-provider.h>
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2011-07-20 22:36:56 -06:00
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#include <linux/delay.h>
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2011-09-07 06:51:50 -06:00
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#include <linux/time.h>
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2011-07-20 22:36:56 -06:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "mxs-saif.h"
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2013-03-28 09:21:16 -06:00
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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2011-07-20 22:36:56 -06:00
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static struct mxs_saif *mxs_saif[2];
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2011-09-07 06:51:50 -06:00
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/*
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* SAIF is a little different with other normal SOC DAIs on clock using.
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*
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* For MXS, two SAIF modules are instantiated on-chip.
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* Each SAIF has a set of clock pins and can be operating in master
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* mode simultaneously if they are connected to different off-chip codecs.
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* Also, one of the two SAIFs can master or drive the clock pins while the
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* other SAIF, in slave mode, receives clocking from the master SAIF.
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* This also means that both SAIFs must operate at the same sample rate.
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*
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* We abstract this as each saif has a master, the master could be
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2013-12-18 06:50:10 -07:00
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* itself or other saifs. In the generic saif driver, saif does not need
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* to know the different clkmux. Saif only needs to know who is its master
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* and operating its master to generate the proper clock rate for it.
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2011-09-07 06:51:50 -06:00
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* The master id is provided in mach-specific layer according to different
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* clkmux setting.
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*/
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2011-07-20 22:36:56 -06:00
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static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
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switch (clk_id) {
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case MXS_SAIF_MCLK:
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saif->mclk = freq;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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2011-09-07 06:51:50 -06:00
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/*
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* Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
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* is provided by other SAIF, we provide a interface here to get its master
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* from its master_id.
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2013-12-18 06:50:10 -07:00
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* Note that the master could be itself.
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2011-09-07 06:51:50 -06:00
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*/
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static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
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{
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return mxs_saif[saif->master_id];
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}
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2011-07-20 22:36:56 -06:00
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/*
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* Set SAIF clock and MCLK
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*/
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static int mxs_saif_set_clk(struct mxs_saif *saif,
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unsigned int mclk,
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unsigned int rate)
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{
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u32 scr;
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int ret;
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2011-09-07 06:51:50 -06:00
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struct mxs_saif *master_saif;
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2011-07-20 22:36:56 -06:00
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2011-09-07 06:51:50 -06:00
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dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
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/* Set master saif to generate proper clock */
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master_saif = mxs_saif_get_master(saif);
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if (!master_saif)
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return -EINVAL;
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dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
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/* Checking if can playback and capture simutaneously */
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if (master_saif->ongoing && rate != master_saif->cur_rate) {
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dev_err(saif->dev,
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"can not change clock, master saif%d(rate %d) is ongoing\n",
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master_saif->id, master_saif->cur_rate);
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return -EINVAL;
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}
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scr = __raw_readl(master_saif->base + SAIF_CTRL);
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2011-07-20 22:36:56 -06:00
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scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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/*
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* Set SAIF clock
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*
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* The SAIF clock should be either 384*fs or 512*fs.
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2017-01-13 13:44:27 -07:00
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* If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
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* For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
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* For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
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2011-07-20 22:36:56 -06:00
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*
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* If MCLK is not used, we just set saif clk to 512*fs.
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*/
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2017-07-25 04:14:33 -06:00
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ret = clk_prepare_enable(master_saif->clk);
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if (ret)
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return ret;
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2012-01-19 05:23:22 -07:00
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2011-09-07 06:51:50 -06:00
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if (master_saif->mclk_in_use) {
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2017-01-13 13:44:27 -07:00
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switch (mclk / rate) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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2011-07-20 22:36:56 -06:00
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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2011-09-07 06:51:50 -06:00
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ret = clk_set_rate(master_saif->clk, 512 * rate);
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2017-01-13 13:44:27 -07:00
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break;
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case 48:
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case 96:
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case 192:
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case 384:
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2011-07-20 22:36:56 -06:00
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scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
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2011-09-07 06:51:50 -06:00
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ret = clk_set_rate(master_saif->clk, 384 * rate);
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2017-01-13 13:44:27 -07:00
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break;
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default:
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/* SAIF MCLK should be a sub-rate of 512x or 384x */
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2012-01-19 05:23:22 -07:00
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clk_disable_unprepare(master_saif->clk);
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2011-07-20 22:36:56 -06:00
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return -EINVAL;
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}
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} else {
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2011-09-07 06:51:50 -06:00
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ret = clk_set_rate(master_saif->clk, 512 * rate);
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2011-07-20 22:36:56 -06:00
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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}
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2012-01-19 05:23:22 -07:00
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clk_disable_unprepare(master_saif->clk);
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2011-07-20 22:36:56 -06:00
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if (ret)
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return ret;
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2011-09-07 06:51:50 -06:00
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master_saif->cur_rate = rate;
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if (!master_saif->mclk_in_use) {
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__raw_writel(scr, master_saif->base + SAIF_CTRL);
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2011-07-20 22:36:56 -06:00
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return 0;
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}
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/*
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* Program the over-sample rate for MCLK output
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*
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* The available MCLK range is 32x, 48x... 512x. The rate
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* could be from 8kHz to 192kH.
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*/
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switch (mclk / rate) {
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case 32:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
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break;
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case 64:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
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break;
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case 128:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
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break;
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case 256:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
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break;
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case 512:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
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break;
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case 48:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
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break;
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case 96:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
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break;
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case 192:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
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break;
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case 384:
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scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
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break;
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default:
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return -EINVAL;
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}
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2011-09-07 06:51:50 -06:00
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__raw_writel(scr, master_saif->base + SAIF_CTRL);
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2011-07-20 22:36:56 -06:00
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return 0;
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}
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/*
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* Put and disable MCLK.
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*/
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int mxs_saif_put_mclk(unsigned int saif_id)
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{
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struct mxs_saif *saif = mxs_saif[saif_id];
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u32 stat;
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if (!saif)
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return -EINVAL;
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stat = __raw_readl(saif->base + SAIF_STAT);
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if (stat & BM_SAIF_STAT_BUSY) {
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dev_err(saif->dev, "error: busy\n");
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return -EBUSY;
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}
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2011-12-19 23:15:44 -07:00
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clk_disable_unprepare(saif->clk);
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2011-07-20 22:36:56 -06:00
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/* disable MCLK output */
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__raw_writel(BM_SAIF_CTRL_CLKGATE,
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saif->base + SAIF_CTRL + MXS_SET_ADDR);
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__raw_writel(BM_SAIF_CTRL_RUN,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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saif->mclk_in_use = 0;
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return 0;
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}
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2012-11-22 05:31:09 -07:00
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EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
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2011-07-20 22:36:56 -06:00
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/*
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* Get MCLK and set clock rate, then enable it
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*
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* This interface is used for codecs who are using MCLK provided
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* by saif.
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*/
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int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
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unsigned int rate)
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{
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struct mxs_saif *saif = mxs_saif[saif_id];
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u32 stat;
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int ret;
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2011-09-07 06:51:50 -06:00
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struct mxs_saif *master_saif;
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2011-07-20 22:36:56 -06:00
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if (!saif)
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return -EINVAL;
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2011-08-21 09:45:40 -06:00
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/* Clear Reset */
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__raw_writel(BM_SAIF_CTRL_SFTRST,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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/* FIXME: need clear clk gate for register r/w */
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__raw_writel(BM_SAIF_CTRL_CLKGATE,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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2011-09-07 06:51:50 -06:00
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master_saif = mxs_saif_get_master(saif);
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if (saif != master_saif) {
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dev_err(saif->dev, "can not get mclk from a non-master saif\n");
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return -EINVAL;
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}
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2011-07-20 22:36:56 -06:00
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stat = __raw_readl(saif->base + SAIF_STAT);
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if (stat & BM_SAIF_STAT_BUSY) {
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dev_err(saif->dev, "error: busy\n");
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return -EBUSY;
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}
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saif->mclk_in_use = 1;
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ret = mxs_saif_set_clk(saif, mclk, rate);
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if (ret)
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return ret;
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2011-12-19 23:15:44 -07:00
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ret = clk_prepare_enable(saif->clk);
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2011-07-20 22:36:56 -06:00
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if (ret)
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return ret;
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/* enable MCLK output */
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__raw_writel(BM_SAIF_CTRL_RUN,
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saif->base + SAIF_CTRL + MXS_SET_ADDR);
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return 0;
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}
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2012-11-22 05:31:09 -07:00
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EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
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2011-07-20 22:36:56 -06:00
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/*
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* SAIF DAI format configuration.
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* Should only be called when port is inactive.
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*/
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static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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u32 scr, stat;
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u32 scr0;
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struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
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stat = __raw_readl(saif->base + SAIF_STAT);
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if (stat & BM_SAIF_STAT_BUSY) {
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dev_err(cpu_dai->dev, "error: busy\n");
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return -EBUSY;
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}
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2017-01-13 13:44:28 -07:00
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/* If SAIF1 is configured as slave, the clk gate needs to be cleared
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* before the register can be written.
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*/
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if (saif->id != saif->master_id) {
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__raw_writel(BM_SAIF_CTRL_SFTRST,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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__raw_writel(BM_SAIF_CTRL_CLKGATE,
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saif->base + SAIF_CTRL + MXS_CLR_ADDR);
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}
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2011-07-20 22:36:56 -06:00
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scr0 = __raw_readl(saif->base + SAIF_CTRL);
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scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
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& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
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|
|
|
scr = 0;
|
|
|
|
|
|
|
|
/* DAI mode */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
/* data frame low 1clk before data */
|
|
|
|
scr |= BM_SAIF_CTRL_DELAY;
|
|
|
|
scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
/* data frame high with data */
|
|
|
|
scr &= ~BM_SAIF_CTRL_DELAY;
|
|
|
|
scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
scr &= ~BM_SAIF_CTRL_JUSTIFY;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DAI clock inversion */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
scr |= BM_SAIF_CTRL_BITCLK_EDGE;
|
|
|
|
scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
scr |= BM_SAIF_CTRL_BITCLK_EDGE;
|
|
|
|
scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
|
|
|
|
scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
|
|
|
|
scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note: We simply just support master mode since SAIF TX can only
|
|
|
|
* work as master.
|
2011-09-07 06:51:50 -06:00
|
|
|
* Here the master is relative to codec side.
|
|
|
|
* Saif internally could be slave when working on EXTMASTER mode.
|
|
|
|
* We just hide this to machine driver.
|
2011-07-20 22:36:56 -06:00
|
|
|
*/
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
2011-09-07 06:51:50 -06:00
|
|
|
if (saif->id == saif->master_id)
|
|
|
|
scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
|
|
|
|
else
|
|
|
|
scr |= BM_SAIF_CTRL_SLAVE_MODE;
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
__raw_writel(scr | scr0, saif->base + SAIF_CTRL);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_saif_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
|
2017-07-25 04:14:33 -06:00
|
|
|
int ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
|
|
|
|
/* clear error status to 0 for each re-open */
|
|
|
|
saif->fifo_underrun = 0;
|
|
|
|
saif->fifo_overrun = 0;
|
|
|
|
|
|
|
|
/* Clear Reset for normal operations */
|
|
|
|
__raw_writel(BM_SAIF_CTRL_SFTRST,
|
|
|
|
saif->base + SAIF_CTRL + MXS_CLR_ADDR);
|
|
|
|
|
2011-08-21 09:45:40 -06:00
|
|
|
/* clear clock gate */
|
|
|
|
__raw_writel(BM_SAIF_CTRL_CLKGATE,
|
|
|
|
saif->base + SAIF_CTRL + MXS_CLR_ADDR);
|
|
|
|
|
2017-07-25 04:14:33 -06:00
|
|
|
ret = clk_prepare(saif->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-01-21 07:55:56 -07:00
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-01-21 07:55:56 -07:00
|
|
|
static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
|
|
|
|
|
clk_unprepare(saif->clk);
|
|
|
|
}
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
/*
|
|
|
|
* Should only be called when port is inactive.
|
|
|
|
* although can be called multiple times by upper layers.
|
|
|
|
*/
|
|
|
|
static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
|
2012-07-20 03:20:24 -06:00
|
|
|
struct mxs_saif *master_saif;
|
2011-07-20 22:36:56 -06:00
|
|
|
u32 scr, stat;
|
|
|
|
int ret;
|
|
|
|
|
2012-07-20 03:20:24 -06:00
|
|
|
master_saif = mxs_saif_get_master(saif);
|
|
|
|
if (!master_saif)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
/* mclk should already be set */
|
|
|
|
if (!saif->mclk && saif->mclk_in_use) {
|
|
|
|
dev_err(cpu_dai->dev, "set mclk first\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
stat = __raw_readl(saif->base + SAIF_STAT);
|
2016-02-03 06:18:20 -07:00
|
|
|
if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
|
2011-07-20 22:36:56 -06:00
|
|
|
dev_err(cpu_dai->dev, "error: busy\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set saif clk based on sample rate.
|
|
|
|
* If mclk is used, we also set mclk, if not, saif->mclk is
|
|
|
|
* default 0, means not used.
|
|
|
|
*/
|
|
|
|
ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
|
|
|
|
if (ret) {
|
|
|
|
dev_err(cpu_dai->dev, "unable to get proper clk\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-07-20 03:20:25 -06:00
|
|
|
if (saif != master_saif) {
|
|
|
|
/*
|
|
|
|
* Set an initial clock rate for the saif internal logic to work
|
|
|
|
* properly. This is important when working in EXTMASTER mode
|
|
|
|
* that uses the other saif's BITCLK&LRCLK but it still needs a
|
|
|
|
* basic clock which should be fast enough for the internal
|
|
|
|
* logic.
|
|
|
|
*/
|
|
|
|
clk_enable(saif->clk);
|
|
|
|
ret = clk_set_rate(saif->clk, 24000000);
|
|
|
|
clk_disable(saif->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-07-25 04:14:33 -06:00
|
|
|
ret = clk_prepare(master_saif->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2012-07-20 03:20:25 -06:00
|
|
|
}
|
2012-07-20 03:20:24 -06:00
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
scr = __raw_readl(saif->base + SAIF_CTRL);
|
|
|
|
|
|
|
|
scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
|
|
|
|
scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
|
|
|
|
switch (params_format(params)) {
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
|
|
scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S20_3LE:
|
|
|
|
scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
|
|
|
|
scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
|
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
|
|
|
scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
|
|
|
|
scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tx/Rx config */
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
/* enable TX mode */
|
|
|
|
scr &= ~BM_SAIF_CTRL_READ_MODE;
|
|
|
|
} else {
|
|
|
|
/* enable RX mode */
|
|
|
|
scr |= BM_SAIF_CTRL_READ_MODE;
|
|
|
|
}
|
|
|
|
|
|
|
|
__raw_writel(scr, saif->base + SAIF_CTRL);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_saif_prepare(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
|
|
|
|
|
|
|
|
/* enable FIFO error irqs */
|
|
|
|
__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
|
|
|
|
saif->base + SAIF_CTRL + MXS_SET_ADDR);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
|
2011-09-07 06:51:50 -06:00
|
|
|
struct mxs_saif *master_saif;
|
|
|
|
u32 delay;
|
2013-10-11 04:11:04 -06:00
|
|
|
int ret;
|
2011-09-07 06:51:50 -06:00
|
|
|
|
|
|
|
master_saif = mxs_saif_get_master(saif);
|
|
|
|
if (!master_saif)
|
|
|
|
return -EINVAL;
|
2011-07-20 22:36:56 -06:00
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2013-10-11 04:11:03 -06:00
|
|
|
if (saif->state == MXS_SAIF_STATE_RUNNING)
|
|
|
|
return 0;
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
dev_dbg(cpu_dai->dev, "start\n");
|
|
|
|
|
2013-10-11 04:11:04 -06:00
|
|
|
ret = clk_enable(master_saif->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(saif->dev, "Failed to enable master clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2011-09-07 06:51:50 -06:00
|
|
|
|
|
|
|
/*
|
2013-12-18 06:50:10 -07:00
|
|
|
* If the saif's master is not itself, we also need to enable
|
2011-09-07 06:51:50 -06:00
|
|
|
* itself clk for its internal basic logic to work.
|
|
|
|
*/
|
|
|
|
if (saif != master_saif) {
|
2013-10-11 04:11:04 -06:00
|
|
|
ret = clk_enable(saif->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(saif->dev, "Failed to enable master clock\n");
|
|
|
|
clk_disable(master_saif->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
__raw_writel(BM_SAIF_CTRL_RUN,
|
|
|
|
saif->base + SAIF_CTRL + MXS_SET_ADDR);
|
2011-09-07 06:51:50 -06:00
|
|
|
}
|
2011-07-20 22:36:56 -06:00
|
|
|
|
2013-10-11 04:11:04 -06:00
|
|
|
if (!master_saif->mclk_in_use)
|
|
|
|
__raw_writel(BM_SAIF_CTRL_RUN,
|
|
|
|
master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
/*
|
2012-11-01 11:57:11 -06:00
|
|
|
* write data to saif data register to trigger
|
|
|
|
* the transfer.
|
|
|
|
* For 24-bit format the 32-bit FIFO register stores
|
|
|
|
* only one channel, so we need to write twice.
|
|
|
|
* This is also safe for the other non 24-bit formats.
|
2011-07-20 22:36:56 -06:00
|
|
|
*/
|
|
|
|
__raw_writel(0, saif->base + SAIF_DATA);
|
2012-11-01 11:57:11 -06:00
|
|
|
__raw_writel(0, saif->base + SAIF_DATA);
|
2011-07-20 22:36:56 -06:00
|
|
|
} else {
|
|
|
|
/*
|
2012-11-01 11:57:11 -06:00
|
|
|
* read data from saif data register to trigger
|
|
|
|
* the receive.
|
|
|
|
* For 24-bit format the 32-bit FIFO register stores
|
|
|
|
* only one channel, so we need to read twice.
|
|
|
|
* This is also safe for the other non 24-bit formats.
|
2011-07-20 22:36:56 -06:00
|
|
|
*/
|
|
|
|
__raw_readl(saif->base + SAIF_DATA);
|
2012-11-01 11:57:11 -06:00
|
|
|
__raw_readl(saif->base + SAIF_DATA);
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
2011-09-07 06:51:50 -06:00
|
|
|
master_saif->ongoing = 1;
|
2013-10-11 04:11:03 -06:00
|
|
|
saif->state = MXS_SAIF_STATE_RUNNING;
|
2011-09-07 06:51:50 -06:00
|
|
|
|
|
|
|
dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
|
2011-07-20 22:36:56 -06:00
|
|
|
__raw_readl(saif->base + SAIF_CTRL),
|
|
|
|
__raw_readl(saif->base + SAIF_STAT));
|
|
|
|
|
2011-09-07 06:51:50 -06:00
|
|
|
dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
|
|
|
|
__raw_readl(master_saif->base + SAIF_CTRL),
|
|
|
|
__raw_readl(master_saif->base + SAIF_STAT));
|
2011-07-20 22:36:56 -06:00
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
2013-10-11 04:11:03 -06:00
|
|
|
if (saif->state == MXS_SAIF_STATE_STOPPED)
|
|
|
|
return 0;
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
dev_dbg(cpu_dai->dev, "stop\n");
|
|
|
|
|
2011-09-07 06:51:50 -06:00
|
|
|
/* wait a while for the current sample to complete */
|
|
|
|
delay = USEC_PER_SEC / master_saif->cur_rate;
|
|
|
|
|
|
|
|
if (!master_saif->mclk_in_use) {
|
|
|
|
__raw_writel(BM_SAIF_CTRL_RUN,
|
|
|
|
master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
|
|
|
|
udelay(delay);
|
|
|
|
}
|
|
|
|
clk_disable(master_saif->clk);
|
|
|
|
|
|
|
|
if (saif != master_saif) {
|
2011-07-20 22:36:56 -06:00
|
|
|
__raw_writel(BM_SAIF_CTRL_RUN,
|
|
|
|
saif->base + SAIF_CTRL + MXS_CLR_ADDR);
|
2011-09-07 06:51:50 -06:00
|
|
|
udelay(delay);
|
|
|
|
clk_disable(saif->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
master_saif->ongoing = 0;
|
2013-10-11 04:11:03 -06:00
|
|
|
saif->state = MXS_SAIF_STATE_STOPPED;
|
2011-07-20 22:36:56 -06:00
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
|
|
|
|
#define MXS_SAIF_FORMATS \
|
|
|
|
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE)
|
|
|
|
|
2011-11-23 03:40:40 -07:00
|
|
|
static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
|
2011-07-20 22:36:56 -06:00
|
|
|
.startup = mxs_saif_startup,
|
2016-01-21 07:55:56 -07:00
|
|
|
.shutdown = mxs_saif_shutdown,
|
2011-07-20 22:36:56 -06:00
|
|
|
.trigger = mxs_saif_trigger,
|
|
|
|
.prepare = mxs_saif_prepare,
|
|
|
|
.hw_params = mxs_saif_hw_params,
|
|
|
|
.set_sysclk = mxs_saif_set_dai_sysclk,
|
|
|
|
.set_fmt = mxs_saif_set_dai_fmt,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = dev_get_drvdata(dai->dev);
|
|
|
|
|
|
|
|
snd_soc_dai_set_drvdata(dai, saif);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_soc_dai_driver mxs_saif_dai = {
|
|
|
|
.name = "mxs-saif",
|
|
|
|
.probe = mxs_saif_dai_probe,
|
|
|
|
.playback = {
|
|
|
|
.channels_min = 2,
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|
|
|
.channels_max = 2,
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.rates = MXS_SAIF_RATES,
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|
|
.formats = MXS_SAIF_FORMATS,
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|
|
|
},
|
|
|
|
.capture = {
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.channels_min = 2,
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|
.channels_max = 2,
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.rates = MXS_SAIF_RATES,
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|
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|
.formats = MXS_SAIF_FORMATS,
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|
|
|
},
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|
.ops = &mxs_saif_dai_ops,
|
|
|
|
};
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|
2013-03-21 04:33:02 -06:00
|
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|
static const struct snd_soc_component_driver mxs_saif_component = {
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|
|
.name = "mxs-saif",
|
|
|
|
};
|
|
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|
|
2011-07-20 22:36:56 -06:00
|
|
|
static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = dev_id;
|
|
|
|
unsigned int stat;
|
|
|
|
|
|
|
|
stat = __raw_readl(saif->base + SAIF_STAT);
|
|
|
|
if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
|
|
|
|
BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
|
|
|
|
dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
|
|
|
|
__raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
|
|
|
|
saif->base + SAIF_STAT + MXS_CLR_ADDR);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
|
|
|
|
dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
|
|
|
|
__raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
|
|
|
|
saif->base + SAIF_STAT + MXS_CLR_ADDR);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
|
|
|
|
__raw_readl(saif->base + SAIF_CTRL),
|
|
|
|
__raw_readl(saif->base + SAIF_STAT));
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2013-07-01 02:16:10 -06:00
|
|
|
static int mxs_saif_mclk_init(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mxs_saif *saif = platform_get_drvdata(pdev);
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct clk *clk;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
|
|
|
|
__clk_get_name(saif->clk), 0,
|
|
|
|
saif->base + SAIF_CTRL,
|
|
|
|
BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
|
|
|
|
0, NULL);
|
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
ret = PTR_ERR(clk);
|
|
|
|
if (ret == -EEXIST)
|
|
|
|
return 0;
|
|
|
|
dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-07 07:26:27 -07:00
|
|
|
static int mxs_saif_probe(struct platform_device *pdev)
|
2011-07-20 22:36:56 -06:00
|
|
|
{
|
2012-05-11 08:24:17 -06:00
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2013-05-12 23:30:56 -06:00
|
|
|
struct resource *iores;
|
2011-07-20 22:36:56 -06:00
|
|
|
struct mxs_saif *saif;
|
2014-12-30 07:11:36 -07:00
|
|
|
int irq, ret = 0;
|
2012-11-14 13:28:58 -07:00
|
|
|
struct device_node *master;
|
2011-07-20 22:36:56 -06:00
|
|
|
|
2012-11-14 13:28:58 -07:00
|
|
|
if (!np)
|
2011-08-21 05:18:45 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
2012-02-10 01:17:01 -07:00
|
|
|
saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
|
2011-07-20 22:36:56 -06:00
|
|
|
if (!saif)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-01-08 05:45:04 -07:00
|
|
|
ret = of_alias_get_id(np, "saif");
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
else
|
|
|
|
saif->id = ret;
|
|
|
|
|
2016-10-14 15:53:36 -06:00
|
|
|
if (saif->id >= ARRAY_SIZE(mxs_saif)) {
|
|
|
|
dev_err(&pdev->dev, "get wrong saif id\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2012-11-14 13:28:58 -07:00
|
|
|
/*
|
|
|
|
* If there is no "fsl,saif-master" phandle, it's a saif
|
|
|
|
* master. Otherwise, it's a slave and its phandle points
|
|
|
|
* to the master.
|
|
|
|
*/
|
|
|
|
master = of_parse_phandle(np, "fsl,saif-master", 0);
|
|
|
|
if (!master) {
|
|
|
|
saif->master_id = saif->id;
|
2011-11-22 08:52:21 -07:00
|
|
|
} else {
|
2013-01-08 05:45:04 -07:00
|
|
|
ret = of_alias_get_id(master, "saif");
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
else
|
|
|
|
saif->master_id = ret;
|
2012-05-11 08:24:17 -06:00
|
|
|
|
2016-10-14 15:53:36 -06:00
|
|
|
if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
|
|
|
|
dev_err(&pdev->dev, "get wrong master id\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-09-07 06:51:50 -06:00
|
|
|
}
|
2011-07-20 22:36:56 -06:00
|
|
|
|
2012-05-11 08:24:17 -06:00
|
|
|
mxs_saif[saif->id] = saif;
|
|
|
|
|
2012-08-06 22:29:43 -06:00
|
|
|
saif->clk = devm_clk_get(&pdev->dev, NULL);
|
2011-07-20 22:36:56 -06:00
|
|
|
if (IS_ERR(saif->clk)) {
|
|
|
|
ret = PTR_ERR(saif->clk);
|
|
|
|
dev_err(&pdev->dev, "Cannot get the clock: %d\n",
|
|
|
|
ret);
|
2012-02-10 01:17:01 -07:00
|
|
|
return ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
2011-10-18 09:06:39 -06:00
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2011-07-20 22:36:56 -06:00
|
|
|
|
2013-01-21 03:09:26 -07:00
|
|
|
saif->base = devm_ioremap_resource(&pdev->dev, iores);
|
|
|
|
if (IS_ERR(saif->base))
|
|
|
|
return PTR_ERR(saif->base);
|
2011-07-20 22:36:56 -06:00
|
|
|
|
2014-12-30 07:11:36 -07:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
2011-07-20 22:36:56 -06:00
|
|
|
dev_err(&pdev->dev, "failed to get irq resource: %d\n",
|
|
|
|
ret);
|
2012-08-06 22:29:43 -06:00
|
|
|
return ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
saif->dev = &pdev->dev;
|
2014-12-30 07:11:36 -07:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
|
2014-11-10 12:49:30 -07:00
|
|
|
dev_name(&pdev->dev), saif);
|
2011-07-20 22:36:56 -06:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
2012-08-06 22:29:43 -06:00
|
|
|
return ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, saif);
|
|
|
|
|
2013-07-01 02:16:10 -06:00
|
|
|
/* We only support saif0 being tx and clock master */
|
|
|
|
if (saif->id == 0) {
|
|
|
|
ret = mxs_saif_mclk_init(pdev);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(&pdev->dev, "failed to init clocks\n");
|
|
|
|
}
|
|
|
|
|
2013-09-16 22:50:09 -06:00
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
|
|
|
|
&mxs_saif_dai, 1);
|
2011-07-20 22:36:56 -06:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "register DAI failed\n");
|
2012-08-06 22:29:43 -06:00
|
|
|
return ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
2012-05-11 08:24:16 -06:00
|
|
|
ret = mxs_pcm_platform_register(&pdev->dev);
|
2011-07-20 22:36:56 -06:00
|
|
|
if (ret) {
|
2012-05-11 08:24:16 -06:00
|
|
|
dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
|
2013-09-16 22:50:09 -06:00
|
|
|
return ret;
|
2011-07-20 22:36:56 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-11 08:24:17 -06:00
|
|
|
static const struct of_device_id mxs_saif_dt_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx28-saif", },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
|
|
|
|
|
2011-07-20 22:36:56 -06:00
|
|
|
static struct platform_driver mxs_saif_driver = {
|
|
|
|
.probe = mxs_saif_probe,
|
|
|
|
|
|
|
|
.driver = {
|
|
|
|
.name = "mxs-saif",
|
2012-05-11 08:24:17 -06:00
|
|
|
.of_match_table = mxs_saif_dt_ids,
|
2011-07-20 22:36:56 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-11-23 23:21:29 -07:00
|
|
|
module_platform_driver(mxs_saif_driver);
|
2011-07-20 22:36:56 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
|
|
MODULE_DESCRIPTION("MXS ASoC SAIF driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
2012-10-30 21:20:05 -06:00
|
|
|
MODULE_ALIAS("platform:mxs-saif");
|