2019-05-27 00:55:06 -06:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2013-03-11 21:38:24 -06:00
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/*
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* Driver for Broadcom BCM2835 SPI Controllers
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*
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* Copyright (C) 2012 Chris Boot
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* Copyright (C) 2013 Stephen Warren
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2015-03-26 04:08:36 -06:00
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* Copyright (C) 2015 Martin Sperl
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2013-03-11 21:38:24 -06:00
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*
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* This driver is inspired by:
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* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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2019-04-23 14:15:13 -06:00
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#include <linux/debugfs.h>
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2013-03-11 21:38:24 -06:00
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#include <linux/delay.h>
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2015-05-10 14:47:28 -06:00
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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2013-03-11 21:38:24 -06:00
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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2015-05-10 14:47:28 -06:00
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#include <linux/of_address.h>
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2013-03-11 21:38:24 -06:00
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#include <linux/of_device.h>
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2019-08-03 18:38:52 -06:00
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#include <linux/gpio/consumer.h>
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#include <linux/gpio/machine.h> /* FIXME: using chip internals */
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#include <linux/gpio/driver.h> /* FIXME: using chip internals */
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2015-05-10 14:47:28 -06:00
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#include <linux/of_irq.h>
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2013-03-11 21:38:24 -06:00
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#include <linux/spi/spi.h>
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/* SPI register offsets */
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#define BCM2835_SPI_CS 0x00
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#define BCM2835_SPI_FIFO 0x04
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#define BCM2835_SPI_CLK 0x08
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#define BCM2835_SPI_DLEN 0x0c
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#define BCM2835_SPI_LTOH 0x10
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#define BCM2835_SPI_DC 0x14
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/* Bitfields in CS */
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#define BCM2835_SPI_CS_LEN_LONG 0x02000000
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#define BCM2835_SPI_CS_DMA_LEN 0x01000000
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#define BCM2835_SPI_CS_CSPOL2 0x00800000
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#define BCM2835_SPI_CS_CSPOL1 0x00400000
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#define BCM2835_SPI_CS_CSPOL0 0x00200000
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#define BCM2835_SPI_CS_RXF 0x00100000
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#define BCM2835_SPI_CS_RXR 0x00080000
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#define BCM2835_SPI_CS_TXD 0x00040000
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#define BCM2835_SPI_CS_RXD 0x00020000
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#define BCM2835_SPI_CS_DONE 0x00010000
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#define BCM2835_SPI_CS_LEN 0x00002000
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#define BCM2835_SPI_CS_REN 0x00001000
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#define BCM2835_SPI_CS_ADCS 0x00000800
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#define BCM2835_SPI_CS_INTR 0x00000400
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#define BCM2835_SPI_CS_INTD 0x00000200
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#define BCM2835_SPI_CS_DMAEN 0x00000100
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#define BCM2835_SPI_CS_TA 0x00000080
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#define BCM2835_SPI_CS_CSPOL 0x00000040
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#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
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#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
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#define BCM2835_SPI_CS_CPOL 0x00000008
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#define BCM2835_SPI_CS_CPHA 0x00000004
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#define BCM2835_SPI_CS_CS_10 0x00000002
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#define BCM2835_SPI_CS_CS_01 0x00000001
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spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
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#define BCM2835_SPI_FIFO_SIZE 64
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#define BCM2835_SPI_FIFO_SIZE_3_4 48
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2015-05-10 14:47:28 -06:00
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#define BCM2835_SPI_DMA_MIN_LENGTH 96
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2015-03-19 03:01:53 -06:00
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_NO_CS | SPI_3WIRE)
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2013-03-11 21:38:24 -06:00
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#define DRV_NAME "spi-bcm2835"
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2019-04-23 14:15:11 -06:00
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/* define polling limits */
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unsigned int polling_limit_us = 30;
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module_param(polling_limit_us, uint, 0664);
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MODULE_PARM_DESC(polling_limit_us,
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"time in us to run a transfer in polling mode\n");
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2018-11-08 00:06:10 -07:00
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/**
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* struct bcm2835_spi - BCM2835 SPI controller
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* @regs: base address of register map
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* @clk: core clock, divided to calculate serial clock
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* @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
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spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
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* @tfr: SPI transfer currently processed
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2018-11-08 00:06:10 -07:00
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* @tx_buf: pointer whence next transmitted byte is read
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* @rx_buf: pointer where next received byte is written
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* @tx_len: remaining bytes to transmit
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* @rx_len: remaining bytes to receive
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spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
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* @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
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* length is not a multiple of 4 (to overcome hardware limitation)
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* @rx_prologue: bytes received without DMA if first RX sglist entry's
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* length is not a multiple of 4 (to overcome hardware limitation)
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* @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
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2018-11-08 00:06:10 -07:00
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* @dma_pending: whether a DMA transfer is in progress
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2019-04-23 14:15:13 -06:00
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* @debugfs_dir: the debugfs directory - neede to remove debugfs when
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* unloading the module
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* @count_transfer_polling: count of how often polling mode is used
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* @count_transfer_irq: count of how often interrupt mode is used
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* @count_transfer_irq_after_polling: count of how often we fall back to
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* interrupt mode after starting in polling mode.
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* These are counted as well in @count_transfer_polling and
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* @count_transfer_irq
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* @count_transfer_dma: count how often dma mode is used
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2018-11-08 00:06:10 -07:00
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*/
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2013-03-11 21:38:24 -06:00
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struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
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struct spi_transfer *tfr;
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2013-03-11 21:38:24 -06:00
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const u8 *tx_buf;
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u8 *rx_buf;
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2015-03-26 04:08:36 -06:00
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int tx_len;
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int rx_len;
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spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
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int tx_prologue;
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int rx_prologue;
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2018-11-29 08:45:24 -07:00
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unsigned int tx_spillover;
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2018-11-29 07:14:49 -07:00
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unsigned int dma_pending;
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2019-04-23 14:15:13 -06:00
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struct dentry *debugfs_dir;
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u64 count_transfer_polling;
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u64 count_transfer_irq;
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u64 count_transfer_irq_after_polling;
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u64 count_transfer_dma;
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2013-03-11 21:38:24 -06:00
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};
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2019-04-23 14:15:13 -06:00
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#if defined(CONFIG_DEBUG_FS)
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static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
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const char *dname)
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{
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char name[64];
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struct dentry *dir;
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/* get full name */
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snprintf(name, sizeof(name), "spi-bcm2835-%s", dname);
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/* the base directory */
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dir = debugfs_create_dir(name, NULL);
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bs->debugfs_dir = dir;
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/* the counters */
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debugfs_create_u64("count_transfer_polling", 0444, dir,
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&bs->count_transfer_polling);
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debugfs_create_u64("count_transfer_irq", 0444, dir,
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&bs->count_transfer_irq);
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debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir,
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&bs->count_transfer_irq_after_polling);
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debugfs_create_u64("count_transfer_dma", 0444, dir,
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&bs->count_transfer_dma);
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}
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static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
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{
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debugfs_remove_recursive(bs->debugfs_dir);
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bs->debugfs_dir = NULL;
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}
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#else
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static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
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const char *dname)
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{
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}
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static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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2013-03-11 21:38:24 -06:00
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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{
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return readl(bs->regs + reg);
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}
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static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
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{
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writel(val, bs->regs + reg);
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}
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2015-03-23 08:11:53 -06:00
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static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
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2013-03-11 21:38:24 -06:00
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{
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u8 byte;
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2015-03-26 04:08:36 -06:00
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while ((bs->rx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
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2013-03-11 21:38:24 -06:00
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byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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if (bs->rx_buf)
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*bs->rx_buf++ = byte;
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2015-03-26 04:08:36 -06:00
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bs->rx_len--;
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2013-03-11 21:38:24 -06:00
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}
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}
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2015-03-23 08:11:53 -06:00
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static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
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2013-03-11 21:38:24 -06:00
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{
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u8 byte;
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2015-03-26 04:08:36 -06:00
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while ((bs->tx_len) &&
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2015-03-23 08:11:53 -06:00
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
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2013-03-11 21:38:24 -06:00
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byte = bs->tx_buf ? *bs->tx_buf++ : 0;
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bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
|
2015-03-26 04:08:36 -06:00
|
|
|
bs->tx_len--;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
/**
|
|
|
|
* bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
* @count: bytes to read from RX FIFO
|
|
|
|
*
|
|
|
|
* The caller must ensure that @bs->rx_len is greater than or equal to @count,
|
|
|
|
* that the RX FIFO contains at least @count bytes and that the DMA Enable flag
|
|
|
|
* in the CS register is set (such that a read from the FIFO register receives
|
2018-11-29 08:45:24 -07:00
|
|
|
* 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
*/
|
|
|
|
static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
|
|
|
|
{
|
|
|
|
u32 val;
|
2018-11-29 08:45:24 -07:00
|
|
|
int len;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
|
|
|
|
bs->rx_len -= count;
|
|
|
|
|
|
|
|
while (count > 0) {
|
|
|
|
val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
|
2018-11-29 08:45:24 -07:00
|
|
|
len = min(count, 4);
|
|
|
|
memcpy(bs->rx_buf, &val, len);
|
|
|
|
bs->rx_buf += len;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
count -= 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
* @count: bytes to write to TX FIFO
|
|
|
|
*
|
|
|
|
* The caller must ensure that @bs->tx_len is greater than or equal to @count,
|
|
|
|
* that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
|
|
|
|
* in the CS register is set (such that a write to the FIFO register transmits
|
|
|
|
* 32-bit instead of just 8-bit).
|
|
|
|
*/
|
|
|
|
static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
|
|
|
|
{
|
|
|
|
u32 val;
|
2018-11-29 08:45:24 -07:00
|
|
|
int len;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
|
|
|
|
bs->tx_len -= count;
|
|
|
|
|
|
|
|
while (count > 0) {
|
|
|
|
if (bs->tx_buf) {
|
2018-11-29 08:45:24 -07:00
|
|
|
len = min(count, 4);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
memcpy(&val, bs->tx_buf, len);
|
|
|
|
bs->tx_buf += len;
|
|
|
|
} else {
|
|
|
|
val = 0;
|
|
|
|
}
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
|
|
|
|
count -= 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
|
|
|
|
* @bs: BCM2835 SPI controller
|
2018-11-29 08:45:24 -07:00
|
|
|
*
|
|
|
|
* The caller must ensure that the RX FIFO can accommodate as many bytes
|
|
|
|
* as have been written to the TX FIFO: Transmission is halted once the
|
|
|
|
* RX FIFO is full, causing this function to spin forever.
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
*/
|
|
|
|
static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
|
|
|
|
{
|
|
|
|
while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
/**
|
|
|
|
* bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
* @count: bytes available for reading in RX FIFO
|
|
|
|
*/
|
|
|
|
static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
count = min(count, bs->rx_len);
|
|
|
|
bs->rx_len -= count;
|
|
|
|
|
|
|
|
while (count) {
|
|
|
|
val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
|
|
|
|
if (bs->rx_buf)
|
|
|
|
*bs->rx_buf++ = val;
|
|
|
|
count--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
* @count: bytes available for writing in TX FIFO
|
|
|
|
*/
|
|
|
|
static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
count = min(count, bs->tx_len);
|
|
|
|
bs->tx_len -= count;
|
|
|
|
|
|
|
|
while (count) {
|
|
|
|
val = bs->tx_buf ? *bs->tx_buf++ : 0;
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
|
|
|
|
count--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static void bcm2835_spi_reset_hw(struct spi_controller *ctlr)
|
2015-03-26 04:08:36 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-03-26 04:08:36 -06:00
|
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
|
|
|
|
|
|
|
/* Disable SPI interrupts and transfer */
|
|
|
|
cs &= ~(BCM2835_SPI_CS_INTR |
|
|
|
|
BCM2835_SPI_CS_INTD |
|
2015-05-10 14:47:28 -06:00
|
|
|
BCM2835_SPI_CS_DMAEN |
|
2015-03-26 04:08:36 -06:00
|
|
|
BCM2835_SPI_CS_TA);
|
|
|
|
/* and reset RX/TX FIFOS */
|
|
|
|
cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
|
|
|
|
|
|
|
|
/* and reset the SPI_HW */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs);
|
2015-05-10 14:47:28 -06:00
|
|
|
/* as well as DLEN */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
|
2015-03-26 04:08:36 -06:00
|
|
|
}
|
|
|
|
|
2013-03-11 21:38:24 -06:00
|
|
|
static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct spi_controller *ctlr = dev_id;
|
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* An interrupt is signaled either if DONE is set (TX FIFO empty)
|
|
|
|
* or if RXR is set (RX FIFO >= ¾ full).
|
|
|
|
*/
|
|
|
|
if (cs & BCM2835_SPI_CS_RXF)
|
|
|
|
bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
|
|
|
|
else if (cs & BCM2835_SPI_CS_RXR)
|
|
|
|
bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
|
|
|
|
|
|
|
|
if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
|
|
|
|
bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2015-03-23 08:11:53 -06:00
|
|
|
/* Read as many bytes as possible from FIFO */
|
|
|
|
bcm2835_rd_fifo(bs);
|
2015-03-26 04:08:36 -06:00
|
|
|
/* Write as many bytes as possible to FIFO */
|
|
|
|
bcm2835_wr_fifo(bs);
|
|
|
|
|
2018-11-08 00:06:10 -07:00
|
|
|
if (!bs->rx_len) {
|
2015-03-26 04:08:36 -06:00
|
|
|
/* Transfer complete - reset SPI HW */
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
2015-03-26 04:08:36 -06:00
|
|
|
/* wake up the framework */
|
2019-05-13 08:48:39 -06:00
|
|
|
complete(&ctlr->xfer_completion);
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2015-03-23 08:11:53 -06:00
|
|
|
return IRQ_HANDLED;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr,
|
2015-04-06 11:16:30 -06:00
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *tfr,
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
u32 cs, bool fifo_empty)
|
2015-04-06 11:16:30 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-04-06 11:16:30 -06:00
|
|
|
|
2019-04-23 14:15:13 -06:00
|
|
|
/* update usage statistics */
|
|
|
|
bs->count_transfer_irq++;
|
|
|
|
|
2015-04-06 11:16:30 -06:00
|
|
|
/*
|
2018-11-08 00:06:10 -07:00
|
|
|
* Enable HW block, but with interrupts still disabled.
|
|
|
|
* Otherwise the empty TX FIFO would immediately trigger an interrupt.
|
2015-04-06 11:16:30 -06:00
|
|
|
*/
|
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
|
|
|
|
|
|
|
|
/* fill TX FIFO as much as possible */
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
if (fifo_empty)
|
|
|
|
bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
|
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_wr_fifo(bs);
|
|
|
|
|
|
|
|
/* enable interrupts */
|
2015-04-06 11:16:30 -06:00
|
|
|
cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs);
|
|
|
|
|
|
|
|
/* signal that we need to wait for completion */
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
/**
|
|
|
|
* bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
|
2019-05-13 08:48:39 -06:00
|
|
|
* @ctlr: SPI master controller
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
* @tfr: SPI transfer
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
* @cs: CS register
|
|
|
|
*
|
|
|
|
* A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
|
|
|
|
* Only the final write access is permitted to transmit less than 4 bytes, the
|
|
|
|
* SPI controller deduces its intended size from the DLEN register.
|
|
|
|
*
|
|
|
|
* If a TX or RX sglist contains multiple entries, one per page, and the first
|
|
|
|
* entry starts in the middle of a page, that first entry's length may not be
|
|
|
|
* a multiple of 4. Subsequent entries are fine because they span an entire
|
|
|
|
* page, hence do have a length that's a multiple of 4.
|
|
|
|
*
|
|
|
|
* This cannot happen with kmalloc'ed buffers (which is what most clients use)
|
|
|
|
* because they are contiguous in physical memory and therefore not split on
|
|
|
|
* page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
|
|
|
|
* buffers.
|
|
|
|
*
|
|
|
|
* The DMA engine is incapable of combining sglist entries into a continuous
|
|
|
|
* stream of 4 byte chunks, it treats every entry separately: A TX entry is
|
|
|
|
* rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
|
|
|
|
* entry is rounded up by throwing away received bytes.
|
|
|
|
*
|
|
|
|
* Overcome this limitation by transferring the first few bytes without DMA:
|
|
|
|
* E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
|
|
|
|
* write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
|
|
|
|
* The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
|
|
|
|
* the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
|
|
|
|
*
|
|
|
|
* Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
|
|
|
|
* write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
|
|
|
|
* Caution, the additional 4 bytes spill over to the second TX sglist entry
|
|
|
|
* if the length of the first is *exactly* 1.
|
|
|
|
*
|
|
|
|
* At most 6 bytes are written and at most 3 bytes read. Do we know the
|
|
|
|
* transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
|
|
|
|
*
|
|
|
|
* The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
|
|
|
|
* by the DMA engine. Toggling the DMA Enable flag in the CS register switches
|
|
|
|
* the width but also garbles the FIFO's contents. The prologue must therefore
|
|
|
|
* be transmitted in 32-bit width to ensure that the following DMA transfer can
|
|
|
|
* pick up the residue in the RX FIFO in ungarbled form.
|
|
|
|
*/
|
2019-05-13 08:48:39 -06:00
|
|
|
static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
struct spi_transfer *tfr,
|
|
|
|
struct bcm2835_spi *bs,
|
|
|
|
u32 cs)
|
|
|
|
{
|
|
|
|
int tx_remaining;
|
|
|
|
|
|
|
|
bs->tfr = tfr;
|
|
|
|
bs->tx_prologue = 0;
|
|
|
|
bs->rx_prologue = 0;
|
|
|
|
bs->tx_spillover = false;
|
|
|
|
|
|
|
|
if (!sg_is_last(&tfr->tx_sg.sgl[0]))
|
|
|
|
bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
|
|
|
|
|
|
|
|
if (!sg_is_last(&tfr->rx_sg.sgl[0])) {
|
|
|
|
bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
|
|
|
|
|
|
|
|
if (bs->rx_prologue > bs->tx_prologue) {
|
|
|
|
if (sg_is_last(&tfr->tx_sg.sgl[0])) {
|
|
|
|
bs->tx_prologue = bs->rx_prologue;
|
|
|
|
} else {
|
|
|
|
bs->tx_prologue += 4;
|
|
|
|
bs->tx_spillover =
|
|
|
|
!(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
|
|
|
|
if (!bs->tx_prologue)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Write and read RX prologue. Adjust first entry in RX sglist. */
|
|
|
|
if (bs->rx_prologue) {
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
|
|
|
|
| BCM2835_SPI_CS_DMAEN);
|
|
|
|
bcm2835_wr_fifo_count(bs, bs->rx_prologue);
|
|
|
|
bcm2835_wait_tx_fifo_empty(bs);
|
|
|
|
bcm2835_rd_fifo_count(bs, bs->rx_prologue);
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
dma_sync_single_for_device(ctlr->dma_rx->device->dev,
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_address(&tfr->rx_sg.sgl[0]),
|
|
|
|
bs->rx_prologue, DMA_FROM_DEVICE);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
|
|
|
|
sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write remaining TX prologue. Adjust first entry in TX sglist.
|
|
|
|
* Also adjust second entry if prologue spills over to it.
|
|
|
|
*/
|
|
|
|
tx_remaining = bs->tx_prologue - bs->rx_prologue;
|
|
|
|
if (tx_remaining) {
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
|
|
|
|
| BCM2835_SPI_CS_DMAEN);
|
|
|
|
bcm2835_wr_fifo_count(bs, tx_remaining);
|
|
|
|
bcm2835_wait_tx_fifo_empty(bs);
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (likely(!bs->tx_spillover)) {
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
|
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
} else {
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
|
|
|
|
sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
|
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* bcm2835_spi_undo_prologue() - reconstruct original sglist state
|
|
|
|
* @bs: BCM2835 SPI controller
|
|
|
|
*
|
|
|
|
* Undo changes which were made to an SPI transfer's sglist when transmitting
|
|
|
|
* the prologue. This is necessary to ensure the same memory ranges are
|
|
|
|
* unmapped that were originally mapped.
|
|
|
|
*/
|
|
|
|
static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
|
|
|
|
{
|
|
|
|
struct spi_transfer *tfr = bs->tfr;
|
|
|
|
|
|
|
|
if (!bs->tx_prologue)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (bs->rx_prologue) {
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
|
|
|
|
sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (likely(!bs->tx_spillover)) {
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
|
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
} else {
|
2018-11-29 08:45:24 -07:00
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
|
|
|
|
sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
|
|
|
|
sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-10 14:47:28 -06:00
|
|
|
static void bcm2835_spi_dma_done(void *data)
|
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct spi_controller *ctlr = data;
|
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* reset fifo and HW */
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* and terminate tx-dma as we do not have an irq for it
|
|
|
|
* because when the rx dma will terminate and this callback
|
|
|
|
* is called the tx-dma must have finished - can't get to this
|
|
|
|
* situation otherwise...
|
|
|
|
*/
|
2018-11-08 00:06:10 -07:00
|
|
|
if (cmpxchg(&bs->dma_pending, true, false)) {
|
2019-05-13 08:48:39 -06:00
|
|
|
dmaengine_terminate_async(ctlr->dma_tx);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_spi_undo_prologue(bs);
|
2018-11-08 00:06:10 -07:00
|
|
|
}
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* and mark as completed */;
|
2019-05-13 08:48:39 -06:00
|
|
|
complete(&ctlr->xfer_completion);
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
2015-05-10 14:47:28 -06:00
|
|
|
struct spi_transfer *tfr,
|
|
|
|
bool is_tx)
|
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct scatterlist *sgl;
|
|
|
|
unsigned int nents;
|
|
|
|
enum dma_transfer_direction dir;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
|
|
|
|
if (is_tx) {
|
|
|
|
dir = DMA_MEM_TO_DEV;
|
2019-05-13 08:48:39 -06:00
|
|
|
chan = ctlr->dma_tx;
|
2015-05-10 14:47:28 -06:00
|
|
|
nents = tfr->tx_sg.nents;
|
|
|
|
sgl = tfr->tx_sg.sgl;
|
|
|
|
flags = 0 /* no tx interrupt */;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
dir = DMA_DEV_TO_MEM;
|
2019-05-13 08:48:39 -06:00
|
|
|
chan = ctlr->dma_rx;
|
2015-05-10 14:47:28 -06:00
|
|
|
nents = tfr->rx_sg.nents;
|
|
|
|
sgl = tfr->rx_sg.sgl;
|
|
|
|
flags = DMA_PREP_INTERRUPT;
|
|
|
|
}
|
|
|
|
/* prepare the channel */
|
|
|
|
desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
|
|
|
|
if (!desc)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* set callback for rx */
|
|
|
|
if (!is_tx) {
|
|
|
|
desc->callback = bcm2835_spi_dma_done;
|
2019-05-13 08:48:39 -06:00
|
|
|
desc->callback_param = ctlr;
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* submit it to DMA-engine */
|
|
|
|
cookie = dmaengine_submit(desc);
|
|
|
|
|
|
|
|
return dma_submit_error(cookie);
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
|
2015-05-10 14:47:28 -06:00
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *tfr,
|
|
|
|
u32 cs)
|
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
int ret;
|
|
|
|
|
2019-04-23 14:15:13 -06:00
|
|
|
/* update usage statistics */
|
|
|
|
bs->count_transfer_dma++;
|
|
|
|
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
/*
|
|
|
|
* Transfer first few bytes without DMA if length of first TX or RX
|
|
|
|
* sglist entry is not a multiple of 4 bytes (hardware limitation).
|
|
|
|
*/
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* setup tx-DMA */
|
2019-05-13 08:48:39 -06:00
|
|
|
ret = bcm2835_spi_prepare_sg(ctlr, tfr, true);
|
2015-05-10 14:47:28 -06:00
|
|
|
if (ret)
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
goto err_reset_hw;
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* start TX early */
|
2019-05-13 08:48:39 -06:00
|
|
|
dma_async_issue_pending(ctlr->dma_tx);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* mark as dma pending */
|
|
|
|
bs->dma_pending = 1;
|
|
|
|
|
|
|
|
/* set the DMA length */
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* start the HW */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS,
|
|
|
|
cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
|
|
|
|
|
|
|
|
/* setup rx-DMA late - to run transfers while
|
|
|
|
* mapping of the rx buffers still takes place
|
|
|
|
* this saves 10us or more.
|
|
|
|
*/
|
2019-05-13 08:48:39 -06:00
|
|
|
ret = bcm2835_spi_prepare_sg(ctlr, tfr, false);
|
2015-05-10 14:47:28 -06:00
|
|
|
if (ret) {
|
|
|
|
/* need to reset on errors */
|
2019-05-13 08:48:39 -06:00
|
|
|
dmaengine_terminate_sync(ctlr->dma_tx);
|
2018-11-08 00:06:10 -07:00
|
|
|
bs->dma_pending = false;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
goto err_reset_hw;
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* start rx dma late */
|
2019-05-13 08:48:39 -06:00
|
|
|
dma_async_issue_pending(ctlr->dma_rx);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* wait for wakeup in framework */
|
|
|
|
return 1;
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
|
|
|
|
err_reset_hw:
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_spi_undo_prologue(bs);
|
|
|
|
return ret;
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
|
2015-05-10 14:47:28 -06:00
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *tfr)
|
|
|
|
{
|
|
|
|
/* we start DMA efforts only on bigger transfers */
|
|
|
|
if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* return OK */
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static void bcm2835_dma_release(struct spi_controller *ctlr)
|
2015-05-10 14:47:28 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
if (ctlr->dma_tx) {
|
|
|
|
dmaengine_terminate_sync(ctlr->dma_tx);
|
|
|
|
dma_release_channel(ctlr->dma_tx);
|
|
|
|
ctlr->dma_tx = NULL;
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
2019-05-13 08:48:39 -06:00
|
|
|
if (ctlr->dma_rx) {
|
|
|
|
dmaengine_terminate_sync(ctlr->dma_rx);
|
|
|
|
dma_release_channel(ctlr->dma_rx);
|
|
|
|
ctlr->dma_rx = NULL;
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev)
|
2015-05-10 14:47:28 -06:00
|
|
|
{
|
|
|
|
struct dma_slave_config slave_config;
|
|
|
|
const __be32 *addr;
|
|
|
|
dma_addr_t dma_reg_base;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* base address in dma-space */
|
2019-05-13 08:48:39 -06:00
|
|
|
addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
|
2015-05-10 14:47:28 -06:00
|
|
|
if (!addr) {
|
|
|
|
dev_err(dev, "could not get DMA-register address - not using dma mode\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
dma_reg_base = be32_to_cpup(addr);
|
|
|
|
|
|
|
|
/* get tx/rx dma */
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
|
|
|
|
if (!ctlr->dma_tx) {
|
2015-05-10 14:47:28 -06:00
|
|
|
dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
|
|
|
|
goto err;
|
|
|
|
}
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
|
|
|
|
if (!ctlr->dma_rx) {
|
2015-05-10 14:47:28 -06:00
|
|
|
dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
|
|
|
|
goto err_release;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* configure DMAs */
|
|
|
|
slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
|
|
|
|
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config);
|
2015-05-10 14:47:28 -06:00
|
|
|
if (ret)
|
|
|
|
goto err_config;
|
|
|
|
|
|
|
|
slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
|
|
|
|
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config);
|
2015-05-10 14:47:28 -06:00
|
|
|
if (ret)
|
|
|
|
goto err_config;
|
|
|
|
|
|
|
|
/* all went well, so set can_dma */
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr->can_dma = bcm2835_spi_can_dma;
|
2015-05-10 14:47:28 -06:00
|
|
|
/* need to do TX AND RX DMA, so we need dummy buffers */
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
err_config:
|
|
|
|
dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
|
|
|
|
ret);
|
|
|
|
err_release:
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_dma_release(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
err:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr,
|
2015-04-22 01:33:03 -06:00
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *tfr,
|
2019-04-23 14:15:08 -06:00
|
|
|
u32 cs)
|
2015-04-22 01:33:03 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-04-22 01:33:03 -06:00
|
|
|
unsigned long timeout;
|
|
|
|
|
2019-04-23 14:15:13 -06:00
|
|
|
/* update usage statistics */
|
|
|
|
bs->count_transfer_polling++;
|
|
|
|
|
2015-04-22 01:33:03 -06:00
|
|
|
/* enable HW block without interrupts */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
|
|
|
|
|
|
|
|
/* fill in the fifo before timeout calculations
|
|
|
|
* if we are interrupted here, then the data is
|
|
|
|
* getting transferred by the HW while we are interrupted
|
|
|
|
*/
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
|
2015-04-22 01:33:03 -06:00
|
|
|
|
2019-04-23 14:15:11 -06:00
|
|
|
/* set the timeout to at least 2 jiffies */
|
|
|
|
timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
|
2015-04-22 01:33:03 -06:00
|
|
|
|
|
|
|
/* loop until finished the transfer */
|
|
|
|
while (bs->rx_len) {
|
|
|
|
/* fill in tx fifo with remaining data */
|
|
|
|
bcm2835_wr_fifo(bs);
|
|
|
|
|
|
|
|
/* read from fifo as much as possible */
|
|
|
|
bcm2835_rd_fifo(bs);
|
|
|
|
|
|
|
|
/* if there is still data pending to read
|
|
|
|
* then check the timeout
|
|
|
|
*/
|
|
|
|
if (bs->rx_len && time_after(jiffies, timeout)) {
|
|
|
|
dev_dbg_ratelimited(&spi->dev,
|
|
|
|
"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
|
|
|
|
jiffies - timeout,
|
|
|
|
bs->tx_len, bs->rx_len);
|
|
|
|
/* fall back to interrupt mode */
|
2019-04-23 14:15:13 -06:00
|
|
|
|
|
|
|
/* update usage statistics */
|
|
|
|
bs->count_transfer_irq_after_polling++;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
return bcm2835_spi_transfer_one_irq(ctlr, spi,
|
spi: bcm2835: Speed up FIFO access if fill level is known
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes
(16 32-bit dwords). The CS register provides hints on their fill level:
"Bit 19 RXR - RX FIFO needs Reading ([¾] full)
0 = RX FIFO is less than [¾] full (or not active TA = 0).
1 = RX FIFO is [¾] or more full. Cleared by reading sufficient
data from the RX FIFO or setting TA to 0."
"Bit 16 DONE - Transfer Done
0 = Transfer is in progress (or not active TA = 0).
1 = Transfer is complete. Cleared by writing more data to the
TX FIFO or setting TA to 0."
"If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...]
If RXR is set read 12 [dwords] data from SPI_FIFO."
[Source: Pages 153, 154 and 158 of
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Note: The spec is missing the "¾" character, presumably due to
copy-pasting from a different charset. It also incorrectly
refers to 16 and 12 "bytes" instead of 32-bit dwords.]
In short, the RXR bit indicates that 48 bytes can be read and the DONE
bit indicates 64 bytes can be written. Leverage this knowledge to read
or write bytes blindly to the FIFO, without polling whether data can be
read or free space is available to write. Moreover, when a transfer is
starting, the TX FIFO is known to be empty, likewise allowing a blind
write of 64 bytes.
This cuts the number of bus accesses in half if the fill level is known.
Also, the (posted) write accesses can be pipelined on the AXI bus since
they are no longer interleaved with (non-posted) reads.
bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time
limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX
FIFO may contain data in this case, but is known to be empty when the
function is called from bcm2835_spi_transfer_one(). Hence only blindly
fill the TX FIFO in the latter case but not the former.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Tested-by: Eric Anholt <eric@anholt.net>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-29 08:45:24 -07:00
|
|
|
tfr, cs, false);
|
2015-04-22 01:33:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Transfer complete - reset SPI HW */
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
2015-04-22 01:33:03 -06:00
|
|
|
/* and return without waiting for completion */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
|
2015-03-26 04:08:36 -06:00
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *tfr)
|
2013-03-11 21:38:24 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2019-04-23 14:15:11 -06:00
|
|
|
unsigned long spi_hz, clk_hz, cdiv, spi_used_hz;
|
|
|
|
unsigned long hz_per_byte, byte_limit;
|
2015-03-26 04:08:36 -06:00
|
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2015-03-26 04:08:36 -06:00
|
|
|
/* set clock */
|
2013-03-11 21:38:24 -06:00
|
|
|
spi_hz = tfr->speed_hz;
|
|
|
|
clk_hz = clk_get_rate(bs->clk);
|
|
|
|
|
|
|
|
if (spi_hz >= clk_hz / 2) {
|
|
|
|
cdiv = 2; /* clk_hz/2 is the fastest we can go */
|
|
|
|
} else if (spi_hz) {
|
2015-03-19 03:01:52 -06:00
|
|
|
/* CDIV must be a multiple of two */
|
|
|
|
cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
|
|
|
|
cdiv += (cdiv % 2);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
|
|
|
if (cdiv >= 65536)
|
|
|
|
cdiv = 0; /* 0 is the slowest we can go */
|
2015-03-20 08:26:11 -06:00
|
|
|
} else {
|
2013-03-11 21:38:24 -06:00
|
|
|
cdiv = 0; /* 0 is the slowest we can go */
|
2015-03-20 08:26:11 -06:00
|
|
|
}
|
2015-04-06 11:16:30 -06:00
|
|
|
spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
|
2015-03-26 04:08:36 -06:00
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2015-07-28 08:03:12 -06:00
|
|
|
/* handle all the 3-wire mode */
|
2019-07-03 04:29:31 -06:00
|
|
|
if (spi->mode & SPI_3WIRE && tfr->rx_buf &&
|
|
|
|
tfr->rx_buf != ctlr->dummy_rx)
|
2015-03-19 03:01:53 -06:00
|
|
|
cs |= BCM2835_SPI_CS_REN;
|
2015-07-28 08:03:12 -06:00
|
|
|
else
|
|
|
|
cs &= ~BCM2835_SPI_CS_REN;
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2018-11-08 00:06:10 -07:00
|
|
|
/*
|
|
|
|
* The driver always uses software-controlled GPIO Chip Select.
|
|
|
|
* Set the hardware-controlled native Chip Select to an invalid
|
|
|
|
* value to prevent it from interfering.
|
2015-03-26 04:08:36 -06:00
|
|
|
*/
|
2018-11-08 00:06:10 -07:00
|
|
|
cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2015-03-26 04:08:36 -06:00
|
|
|
/* set transmit buffers and length */
|
2013-03-11 21:38:24 -06:00
|
|
|
bs->tx_buf = tfr->tx_buf;
|
|
|
|
bs->rx_buf = tfr->rx_buf;
|
2015-03-26 04:08:36 -06:00
|
|
|
bs->tx_len = tfr->len;
|
|
|
|
bs->rx_len = tfr->len;
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-04-23 14:15:09 -06:00
|
|
|
/* Calculate the estimated time in us the transfer runs. Note that
|
|
|
|
* there is 1 idle clocks cycles after each byte getting transferred
|
|
|
|
* so we have 9 cycles/byte. This is used to find the number of Hz
|
|
|
|
* per byte per polling limit. E.g., we can transfer 1 byte in 30 us
|
|
|
|
* per 300,000 Hz of bus clock.
|
|
|
|
*/
|
2019-04-23 14:15:11 -06:00
|
|
|
hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
|
|
|
|
byte_limit = hz_per_byte ? spi_used_hz / hz_per_byte : 1;
|
|
|
|
|
2019-04-23 14:15:09 -06:00
|
|
|
/* run in polling mode for short transfers */
|
2019-04-23 14:15:11 -06:00
|
|
|
if (tfr->len < byte_limit)
|
2019-05-13 08:48:39 -06:00
|
|
|
return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-04-23 14:15:10 -06:00
|
|
|
/* run in dma mode if conditions are right
|
|
|
|
* Note that unlike poll or interrupt mode DMA mode does not have
|
|
|
|
* this 1 idle clock cycle pattern but runs the spi clock without gaps
|
|
|
|
*/
|
2019-05-13 08:48:39 -06:00
|
|
|
if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
|
|
|
|
return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* run in interrupt-mode */
|
2019-05-13 08:48:39 -06:00
|
|
|
return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
|
2015-07-28 08:03:12 -06:00
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct spi_device *spi = msg->spi;
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-07-28 08:03:12 -06:00
|
|
|
u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
|
2019-04-13 12:24:14 -06:00
|
|
|
int ret;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
if (ctlr->can_dma) {
|
2019-05-09 08:39:59 -06:00
|
|
|
/*
|
|
|
|
* DMA transfers are limited to 16 bit (0 to 65535 bytes) by
|
|
|
|
* the SPI HW due to DLEN. Split up transfers (32-bit FIFO
|
|
|
|
* aligned) if the limit is exceeded.
|
|
|
|
*/
|
2019-05-13 08:48:39 -06:00
|
|
|
ret = spi_split_transfers_maxsize(ctlr, msg, 65532,
|
2019-05-09 08:39:59 -06:00
|
|
|
GFP_KERNEL | GFP_DMA);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2015-07-28 08:03:12 -06:00
|
|
|
|
|
|
|
cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
|
|
|
|
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
cs |= BCM2835_SPI_CS_CPOL;
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
cs |= BCM2835_SPI_CS_CPHA;
|
|
|
|
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS, cs);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
static void bcm2835_spi_handle_err(struct spi_controller *ctlr,
|
2015-03-26 04:08:36 -06:00
|
|
|
struct spi_message *msg)
|
2013-03-11 21:38:24 -06:00
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
|
|
|
/* if an error occurred and we have an active dma, then terminate */
|
2018-11-08 00:06:10 -07:00
|
|
|
if (cmpxchg(&bs->dma_pending, true, false)) {
|
2019-05-13 08:48:39 -06:00
|
|
|
dmaengine_terminate_sync(ctlr->dma_tx);
|
|
|
|
dmaengine_terminate_sync(ctlr->dma_rx);
|
spi: bcm2835: Overcome sglist entry length limitation
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is
accessed in 4 byte chunks. This rule is not fulfilled if a transfer
consists of multiple sglist entries, one per page, and the first entry
starts in the middle of a page with an offset not a multiple of 4.
The driver currently falls back to programmed I/O for such transfers,
incurring a significant performance penalty.
Overcome this hardware limitation by transferring the first few bytes of
a transfer without DMA such that the remainder of the first sglist entry
becomes a multiple of 4. Specifics are provided in kerneldoc comments.
An alternative approach would have been to split transfers in the
->prepare_message hook, but this may necessitate two transfers per page,
defeating the goal of clustering multiple pages together in a single
transfer for efficiency. E.g. if the first TX sglist entry's length is
23 and the first RX's is 40, the first transfer would send and receive
23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079
bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words,
O(n) transfers are necessary (n = number of sglist entries), whereas
the algorithm implemented herein only requires O(1) additional work.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Frank Pavlic <f.pavlic@kunbus.de>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-08 00:06:10 -07:00
|
|
|
bcm2835_spi_undo_prologue(bs);
|
2015-05-10 14:47:28 -06:00
|
|
|
}
|
|
|
|
/* and reset */
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_spi_reset_hw(ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2015-04-06 11:16:31 -06:00
|
|
|
static int chip_match_name(struct gpio_chip *chip, void *data)
|
|
|
|
{
|
|
|
|
return !strcmp(chip->label, data);
|
|
|
|
}
|
|
|
|
|
2015-03-26 04:08:36 -06:00
|
|
|
static int bcm2835_spi_setup(struct spi_device *spi)
|
|
|
|
{
|
2015-04-06 11:16:31 -06:00
|
|
|
struct gpio_chip *chip;
|
2019-08-03 18:38:52 -06:00
|
|
|
enum gpio_lookup_flags lflags;
|
|
|
|
|
2015-03-26 04:08:36 -06:00
|
|
|
/*
|
|
|
|
* sanity checking the native-chipselects
|
|
|
|
*/
|
|
|
|
if (spi->mode & SPI_NO_CS)
|
|
|
|
return 0;
|
2019-08-03 18:38:52 -06:00
|
|
|
/*
|
|
|
|
* The SPI core has successfully requested the CS GPIO line from the
|
|
|
|
* device tree, so we are done.
|
|
|
|
*/
|
|
|
|
if (spi->cs_gpiod)
|
2015-03-26 04:08:36 -06:00
|
|
|
return 0;
|
2015-04-06 11:16:31 -06:00
|
|
|
if (spi->chip_select > 1) {
|
|
|
|
/* error in the case of native CS requested with CS > 1
|
|
|
|
* officially there is a CS2, but it is not documented
|
|
|
|
* which GPIO is connected with that...
|
|
|
|
*/
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
"setup: only two native chip-selects are supported\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2019-08-03 18:38:52 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Translate native CS to GPIO
|
|
|
|
*
|
|
|
|
* FIXME: poking around in the gpiolib internals like this is
|
|
|
|
* not very good practice. Find a way to locate the real problem
|
|
|
|
* and fix it. Why is the GPIO descriptor in spi->cs_gpiod
|
|
|
|
* sometimes not assigned correctly? Erroneous device trees?
|
|
|
|
*/
|
2015-04-06 11:16:31 -06:00
|
|
|
|
|
|
|
/* get the gpio chip for the base */
|
|
|
|
chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
|
|
|
|
if (!chip)
|
2015-03-26 04:08:36 -06:00
|
|
|
return 0;
|
|
|
|
|
2019-08-03 18:38:52 -06:00
|
|
|
/*
|
|
|
|
* Retrieve the corresponding GPIO line used for CS.
|
|
|
|
* The inversion semantics will be handled by the GPIO core
|
|
|
|
* code, so we pass GPIOS_OUT_LOW for "unasserted" and
|
|
|
|
* the correct flag for inversion semantics. The SPI_CS_HIGH
|
|
|
|
* on spi->mode cannot be checked for polarity in this case
|
|
|
|
* as the flag use_gpio_descriptors enforces SPI_CS_HIGH.
|
|
|
|
*/
|
|
|
|
if (of_property_read_bool(spi->dev.of_node, "spi-cs-high"))
|
|
|
|
lflags = GPIO_ACTIVE_HIGH;
|
|
|
|
else
|
|
|
|
lflags = GPIO_ACTIVE_LOW;
|
|
|
|
spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
|
|
|
|
DRV_NAME,
|
|
|
|
lflags,
|
|
|
|
GPIOD_OUT_LOW);
|
|
|
|
if (IS_ERR(spi->cs_gpiod))
|
|
|
|
return PTR_ERR(spi->cs_gpiod);
|
2015-04-06 11:16:31 -06:00
|
|
|
|
|
|
|
/* and set up the "mode" and level */
|
2019-08-03 18:38:52 -06:00
|
|
|
dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
|
|
|
|
spi->chip_select);
|
2015-04-06 11:16:31 -06:00
|
|
|
|
|
|
|
return 0;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm2835_spi_probe(struct platform_device *pdev)
|
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct spi_controller *ctlr;
|
2013-03-11 21:38:24 -06:00
|
|
|
struct bcm2835_spi *bs;
|
|
|
|
int err;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr = spi_alloc_master(&pdev->dev, sizeof(*bs));
|
|
|
|
if (!ctlr)
|
2013-03-11 21:38:24 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
platform_set_drvdata(pdev, ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-08-03 18:38:52 -06:00
|
|
|
ctlr->use_gpio_descriptors = true;
|
2019-05-13 08:48:39 -06:00
|
|
|
ctlr->mode_bits = BCM2835_SPI_MODE_BITS;
|
|
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
|
|
ctlr->num_chipselect = 3;
|
|
|
|
ctlr->setup = bcm2835_spi_setup;
|
|
|
|
ctlr->transfer_one = bcm2835_spi_transfer_one;
|
|
|
|
ctlr->handle_err = bcm2835_spi_handle_err;
|
|
|
|
ctlr->prepare_message = bcm2835_spi_prepare_message;
|
|
|
|
ctlr->dev.of_node = pdev->dev.of_node;
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
bs = spi_controller_get_devdata(ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-09-04 07:58:48 -06:00
|
|
|
bs->regs = devm_platform_ioremap_resource(pdev, 0);
|
2013-05-02 06:13:30 -06:00
|
|
|
if (IS_ERR(bs->regs)) {
|
|
|
|
err = PTR_ERR(bs->regs);
|
2019-05-13 08:48:39 -06:00
|
|
|
goto out_controller_put;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
bs->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(bs->clk)) {
|
|
|
|
err = PTR_ERR(bs->clk);
|
|
|
|
dev_err(&pdev->dev, "could not get clk: %d\n", err);
|
2019-05-13 08:48:39 -06:00
|
|
|
goto out_controller_put;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2015-10-15 04:09:11 -06:00
|
|
|
bs->irq = platform_get_irq(pdev, 0);
|
2013-03-11 21:38:24 -06:00
|
|
|
if (bs->irq <= 0) {
|
|
|
|
err = bs->irq ? bs->irq : -ENODEV;
|
2019-05-13 08:48:39 -06:00
|
|
|
goto out_controller_put;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
clk_prepare_enable(bs->clk);
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_dma_init(ctlr, &pdev->dev);
|
2015-10-15 04:09:11 -06:00
|
|
|
|
|
|
|
/* initialise the hardware with the default polarities */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS,
|
|
|
|
BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
|
|
|
|
|
2013-12-09 03:25:00 -07:00
|
|
|
err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
|
2019-05-13 08:48:39 -06:00
|
|
|
dev_name(&pdev->dev), ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
|
|
|
|
goto out_clk_disable;
|
|
|
|
}
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
err = devm_spi_register_controller(&pdev->dev, ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
if (err) {
|
2019-05-13 08:48:39 -06:00
|
|
|
dev_err(&pdev->dev, "could not register SPI controller: %d\n",
|
|
|
|
err);
|
2013-12-09 03:25:00 -07:00
|
|
|
goto out_clk_disable;
|
2013-03-11 21:38:24 -06:00
|
|
|
}
|
|
|
|
|
2019-04-23 14:15:13 -06:00
|
|
|
bcm2835_debugfs_create(bs, dev_name(&pdev->dev));
|
|
|
|
|
2013-03-11 21:38:24 -06:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_clk_disable:
|
|
|
|
clk_disable_unprepare(bs->clk);
|
2019-05-13 08:48:39 -06:00
|
|
|
out_controller_put:
|
|
|
|
spi_controller_put(ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm2835_spi_remove(struct platform_device *pdev)
|
|
|
|
{
|
2019-05-13 08:48:39 -06:00
|
|
|
struct spi_controller *ctlr = platform_get_drvdata(pdev);
|
|
|
|
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
2013-03-11 21:38:24 -06:00
|
|
|
|
2019-04-23 14:15:13 -06:00
|
|
|
bcm2835_debugfs_remove(bs);
|
|
|
|
|
2013-03-11 21:38:24 -06:00
|
|
|
/* Clear FIFOs, and disable the HW block */
|
|
|
|
bcm2835_wr(bs, BCM2835_SPI_CS,
|
|
|
|
BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
|
|
|
|
|
|
|
|
clk_disable_unprepare(bs->clk);
|
|
|
|
|
2019-05-13 08:48:39 -06:00
|
|
|
bcm2835_dma_release(ctlr);
|
2015-05-10 14:47:28 -06:00
|
|
|
|
2013-03-11 21:38:24 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id bcm2835_spi_match[] = {
|
|
|
|
{ .compatible = "brcm,bcm2835-spi", },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
|
|
|
|
|
|
|
|
static struct platform_driver bcm2835_spi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.of_match_table = bcm2835_spi_match,
|
|
|
|
},
|
|
|
|
.probe = bcm2835_spi_probe,
|
|
|
|
.remove = bcm2835_spi_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(bcm2835_spi_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
|
|
|
|
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
|
2018-10-23 05:06:08 -06:00
|
|
|
MODULE_LICENSE("GPL");
|