2005-04-16 16:20:36 -06:00
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/*
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* Setup pointers to hardware-dependent routines.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 98, 2000, 03, 04 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/config.h>
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#include <linux/eisa.h>
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#include <linux/hdreg.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <linux/pci.h>
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#include <linux/console.h>
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#include <linux/fb.h>
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#include <linux/tty.h>
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#include <asm/arc/types.h>
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#include <asm/sgialib.h>
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mc146818-time.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/reboot.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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extern void sni_machine_restart(char *command);
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extern void sni_machine_halt(void);
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extern void sni_machine_power_off(void);
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static void __init sni_rm200_pci_timer_setup(struct irqaction *irq)
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{
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/* set the clock to 100 Hz */
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outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
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outb_p(LATCH & 0xff , 0x40); /* LSB */
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outb(LATCH >> 8 , 0x40); /* MSB */
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setup_irq(0, irq);
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}
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/*
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* A bit more gossip about the iron we're running on ...
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*/
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static inline void sni_pcimt_detect(void)
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{
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char boardtype[80];
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unsigned char csmsr;
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char *p = boardtype;
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unsigned int asic;
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csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
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p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
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if ((csmsr & 0x80) == 0)
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p += sprintf(p, ", board revision %s",
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(csmsr & 0x20) ? "D" : "C");
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asic = csmsr & 0x80;
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asic = (csmsr & 0x08) ? asic : !asic;
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p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
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printk("%s.\n", boardtype);
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}
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static void __init sni_display_setup(void)
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{
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#ifdef CONFIG_VT
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#if defined(CONFIG_VGA_CONSOLE)
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struct screen_info *si = &screen_info;
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DISPLAY_STATUS *di;
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di = ArcGetDisplayStatus(1);
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if (di) {
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si->orig_x = di->CursorXPosition;
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si->orig_y = di->CursorYPosition;
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si->orig_video_cols = di->CursorMaxXPosition;
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si->orig_video_lines = di->CursorMaxYPosition;
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si->orig_video_isVGA = VIDEO_TYPE_VGAC;
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si->orig_video_points = 16;
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}
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#endif
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#endif
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}
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static struct resource sni_io_resource = {
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"PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO,
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};
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static struct resource pcimt_io_resources[] = {
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{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
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{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
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{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
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{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
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{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
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{ "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY }
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};
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static struct resource sni_mem_resource = {
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"PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM
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};
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/*
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* The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
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* for other purposes. Be paranoid and allocate all of the before the PCI
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* code gets a chance to to map anything else there ...
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2005-09-03 16:56:17 -06:00
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*
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2005-04-16 16:20:36 -06:00
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* This leaves the following areas available:
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*
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* 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
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* 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
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* 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
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* 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
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* 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
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*/
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static struct resource pcimt_mem_resources[] = {
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{ "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY },
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{ "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY },
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{ "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY },
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{ "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY},
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{ "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY },
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{ "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY},
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{ "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY},
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{ "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY},
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{ "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY},
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{ "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY},
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{ "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY},
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{ "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY},
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{ "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY}
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};
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static void __init sni_resource_init(void)
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{
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int i;
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/* request I/O space for devices used on all i[345]86 PCs */
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for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
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request_resource(&ioport_resource, pcimt_io_resources + i);
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/* request mem space for pcimt-specific devices */
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for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
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request_resource(&sni_mem_resource, pcimt_mem_resources + i);
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ioport_resource.end = sni_io_resource.end;
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}
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extern struct pci_ops sni_pci_ops;
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static struct pci_controller sni_controller = {
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.pci_ops = &sni_pci_ops,
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.mem_resource = &sni_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_resource = &sni_io_resource,
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.io_offset = 0x00000000UL
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};
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static inline void sni_pcimt_time_init(void)
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{
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rtc_get_time = mc146818_get_cmos_time;
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rtc_set_time = mc146818_set_rtc_mmss;
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}
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static int __init sni_rm200_pci_setup(void)
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{
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sni_pcimt_detect();
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sni_pcimt_sc_init();
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sni_pcimt_time_init();
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set_io_port_base(SNI_PORT_BASE);
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ioport_resource.end = sni_io_resource.end;
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/*
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* Setup (E)ISA I/O memory access stuff
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*/
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isa_slot_offset = 0xb0000000;
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#ifdef CONFIG_EISA
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EISA_bus = 1;
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#endif
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sni_resource_init();
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board_timer_setup = sni_rm200_pci_timer_setup;
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_machine_restart = sni_machine_restart;
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_machine_halt = sni_machine_halt;
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_machine_power_off = sni_machine_power_off;
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sni_display_setup();
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#ifdef CONFIG_PCI
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register_pci_controller(&sni_controller);
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#endif
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return 0;
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}
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early_initcall(sni_rm200_pci_setup);
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