2005-11-10 07:26:51 -07:00
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/*
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* linux/arch/arm/mach-omap2/io.c
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*
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* OMAP2 I/O mapping code
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*
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* Copyright (C) 2005 Nokia Corporation
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2009-05-28 15:16:04 -06:00
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* Copyright (C) 2007-2009 Texas Instruments
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2008-10-06 06:49:36 -06:00
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*
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* Author:
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* Juha Yrjola <juha.yrjola@nokia.com>
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* Syed Khasim <x0khasim@ti.com>
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2005-11-10 07:26:51 -07:00
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*
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2009-05-28 15:16:04 -06:00
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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2005-11-10 07:26:51 -07:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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2008-09-06 05:10:45 -06:00
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#include <linux/io.h>
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2009-06-19 19:08:25 -06:00
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#include <linux/clk.h>
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2009-08-03 06:06:36 -06:00
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#include <linux/omapfb.h>
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2005-11-10 07:26:51 -07:00
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2006-04-02 10:46:27 -06:00
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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2009-10-20 10:40:47 -06:00
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#include <plat/mux.h>
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#include <plat/sram.h>
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#include <plat/sdrc.h>
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#include <plat/gpmc.h>
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#include <plat/serial.h>
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2009-08-07 03:01:55 -06:00
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#include <plat/vram.h>
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2008-10-06 06:49:36 -06:00
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#include "clock.h"
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2005-11-10 07:26:51 -07:00
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2009-10-20 10:40:47 -06:00
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#include <plat/omap-pm.h>
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#include <plat/powerdomain.h>
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2008-08-19 02:08:40 -06:00
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#include "powerdomains.h"
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2005-11-10 07:26:51 -07:00
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2009-10-20 10:40:47 -06:00
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#include <plat/clockdomain.h>
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2008-08-19 02:08:44 -06:00
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#include "clockdomains.h"
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2009-10-20 10:40:47 -06:00
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#include <plat/omap_hwmod.h>
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2009-09-03 11:14:05 -06:00
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#include "omap_hwmod_2420.h"
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#include "omap_hwmod_2430.h"
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#include "omap_hwmod_34xx.h"
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2005-11-10 07:26:51 -07:00
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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2008-10-09 08:51:41 -06:00
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#ifdef CONFIG_ARCH_OMAP24XX
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static struct map_desc omap24xx_io_desc[] __initdata = {
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2005-11-10 07:26:51 -07:00
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{
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.virtual = L3_24XX_VIRT,
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.pfn = __phys_to_pfn(L3_24XX_PHYS),
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.length = L3_24XX_SIZE,
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.type = MT_DEVICE
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},
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2008-02-20 16:30:06 -07:00
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{
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2008-10-09 08:51:41 -06:00
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.virtual = L4_24XX_VIRT,
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.pfn = __phys_to_pfn(L4_24XX_PHYS),
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.length = L4_24XX_SIZE,
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.type = MT_DEVICE
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2008-02-20 16:30:06 -07:00
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},
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2008-10-09 08:51:41 -06:00
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};
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#ifdef CONFIG_ARCH_OMAP2420
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static struct map_desc omap242x_io_desc[] __initdata = {
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{
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.virtual = DSP_MEM_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
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.length = DSP_MEM_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_IPI_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
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.length = DSP_IPI_24XX_SIZE,
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.type = MT_DEVICE
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2008-02-20 16:30:06 -07:00
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},
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2008-10-09 08:51:41 -06:00
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{
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.virtual = DSP_MMU_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
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.length = DSP_MMU_24XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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2006-12-06 18:14:05 -07:00
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#ifdef CONFIG_ARCH_OMAP2430
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2008-10-09 08:51:41 -06:00
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static struct map_desc omap243x_io_desc[] __initdata = {
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2006-12-06 18:14:05 -07:00
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{
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.virtual = L4_WK_243X_VIRT,
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.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
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.length = L4_WK_243X_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
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.length = OMAP243X_GPMC_SIZE,
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.type = MT_DEVICE
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},
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2008-10-09 08:51:41 -06:00
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{
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.virtual = OMAP243X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
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.length = OMAP243X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
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.length = OMAP243X_SMS_SIZE,
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.type = MT_DEVICE
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},
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};
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2006-12-06 18:14:05 -07:00
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#endif
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#endif
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2008-10-09 08:51:41 -06:00
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#ifdef CONFIG_ARCH_OMAP34XX
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static struct map_desc omap34xx_io_desc[] __initdata = {
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2005-11-10 07:26:51 -07:00
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{
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2008-10-09 08:51:41 -06:00
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.virtual = L3_34XX_VIRT,
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.pfn = __phys_to_pfn(L3_34XX_PHYS),
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.length = L3_34XX_SIZE,
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2006-12-07 14:58:10 -07:00
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.type = MT_DEVICE
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},
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{
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2008-10-09 08:51:41 -06:00
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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2006-12-07 14:58:10 -07:00
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.type = MT_DEVICE
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},
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{
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2008-10-09 08:51:41 -06:00
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.virtual = L4_WK_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
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.length = L4_WK_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP34XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
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.length = OMAP34XX_GPMC_SIZE,
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2005-11-10 07:26:51 -07:00
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.type = MT_DEVICE
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2008-10-09 08:51:41 -06:00
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},
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{
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.virtual = OMAP343X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
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.length = OMAP343X_SMS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
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.length = OMAP343X_SDRC_SIZE,
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2005-11-10 07:26:51 -07:00
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.type = MT_DEVICE
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2008-10-09 08:51:41 -06:00
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},
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{
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.virtual = L4_PER_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
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.length = L4_PER_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_EMU_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
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.length = L4_EMU_34XX_SIZE,
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.type = MT_DEVICE
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},
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2005-11-10 07:26:51 -07:00
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};
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2008-10-09 08:51:41 -06:00
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#endif
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2009-05-28 15:16:04 -06:00
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#ifdef CONFIG_ARCH_OMAP4
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static struct map_desc omap44xx_io_desc[] __initdata = {
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{
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.virtual = L3_44XX_VIRT,
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.pfn = __phys_to_pfn(L3_44XX_PHYS),
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.length = L3_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_44XX_PHYS),
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.length = L4_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_WK_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
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.length = L4_WK_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
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.length = OMAP44XX_GPMC_SIZE,
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.type = MT_DEVICE,
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},
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2009-10-19 18:25:57 -06:00
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{
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.virtual = OMAP44XX_EMIF1_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
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.length = OMAP44XX_EMIF1_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_EMIF2_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
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.length = OMAP44XX_EMIF2_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_DMM_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
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.length = OMAP44XX_DMM_SIZE,
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.type = MT_DEVICE,
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},
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2009-05-28 15:16:04 -06:00
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{
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.virtual = L4_PER_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
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.length = L4_PER_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_EMU_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
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.length = L4_EMU_44XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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2005-11-10 07:26:51 -07:00
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2006-04-02 10:46:27 -06:00
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void __init omap2_map_common_io(void)
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2005-11-10 07:26:51 -07:00
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{
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2008-10-09 08:51:41 -06:00
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#if defined(CONFIG_ARCH_OMAP2420)
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
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#endif
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#if defined(CONFIG_ARCH_OMAP2430)
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
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#endif
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#if defined(CONFIG_ARCH_OMAP34XX)
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iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
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#endif
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2006-04-02 10:46:27 -06:00
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2009-05-28 15:16:04 -06:00
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#if defined(CONFIG_ARCH_OMAP4)
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iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
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#endif
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2006-04-02 10:46:27 -06:00
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/* Normally devicemaps_init() would flush caches and tlb after
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* mdesc->map_io(), but we must also do it here because of the CPU
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* revision check below.
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*/
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local_flush_tlb_all();
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flush_cache_all();
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2005-11-10 07:26:51 -07:00
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omap2_check_revision();
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omap_sram_init();
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2007-03-06 04:16:36 -07:00
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omapfb_reserve_sdram();
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2009-08-07 03:01:55 -06:00
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omap_vram_reserve_sdram();
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2006-04-02 10:46:27 -06:00
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}
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2009-06-19 19:08:25 -06:00
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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* Sets the CORE DPLL3 M2 divider to the same value that it's at
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* currently. This has the effect of setting the SDRC SDRAM AC timing
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* registers to the values currently defined by the kernel. Currently
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* only defined for OMAP3; will return 0 if called on OMAP2. Returns
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* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
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* or passes along the return value of clk_set_rate().
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*/
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static int __init _omap2_init_reprogram_sdrc(void)
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{
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struct clk *dpll3_m2_ck;
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int v = -EINVAL;
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long rate;
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if (!cpu_is_omap34xx())
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return 0;
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dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
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if (!dpll3_m2_ck)
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return -EINVAL;
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rate = clk_get_rate(dpll3_m2_ck);
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pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
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v = clk_set_rate(dpll3_m2_ck, rate);
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if (v)
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pr_err("dpll3_m2_clk rate change failed: %d\n", v);
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clk_put(dpll3_m2_ck);
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return v;
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}
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2009-07-24 19:43:25 -06:00
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void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
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struct omap_sdrc_params *sdrc_cs1)
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2006-04-02 10:46:27 -06:00
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{
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2009-09-03 11:14:05 -06:00
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struct omap_hwmod **hwmods = NULL;
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if (cpu_is_omap2420())
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hwmods = omap2420_hwmods;
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else if (cpu_is_omap2430())
|
|
|
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hwmods = omap2430_hwmods;
|
|
|
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else if (cpu_is_omap34xx())
|
|
|
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hwmods = omap34xx_hwmods;
|
|
|
|
|
2009-05-28 15:16:04 -06:00
|
|
|
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
|
2009-09-03 11:14:01 -06:00
|
|
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/* The OPP tables have to be registered before a clk init */
|
2009-09-24 17:23:07 -06:00
|
|
|
omap_hwmod_init(hwmods);
|
|
|
|
omap2_mux_init();
|
2009-09-03 11:14:01 -06:00
|
|
|
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
|
2008-08-19 02:08:40 -06:00
|
|
|
pwrdm_init(powerdomains_omap);
|
2008-08-19 02:08:44 -06:00
|
|
|
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
|
2009-10-22 15:48:14 -06:00
|
|
|
#endif
|
2009-12-08 11:31:44 -07:00
|
|
|
omap2_clk_init();
|
2009-09-03 11:14:02 -06:00
|
|
|
omap_serial_early_init();
|
2009-10-22 15:48:14 -06:00
|
|
|
#ifndef CONFIG_ARCH_OMAP4
|
2009-09-03 11:14:05 -06:00
|
|
|
omap_hwmod_late_init();
|
2009-09-03 11:14:01 -06:00
|
|
|
omap_pm_if_init();
|
2009-07-24 19:43:25 -06:00
|
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
2009-06-19 19:08:25 -06:00
|
|
|
_omap2_init_reprogram_sdrc();
|
2009-05-28 15:16:04 -06:00
|
|
|
#endif
|
2006-06-26 17:16:16 -06:00
|
|
|
gpmc_init();
|
2005-11-10 07:26:51 -07:00
|
|
|
}
|