2008-04-25 05:55:19 -06:00
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/*
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* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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2009-04-17 05:42:26 -06:00
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* Contact: Jarkko Nikula <jhnikula@gmail.com>
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* Peter Ujfalusi <peter.ujfalusi@nokia.com>
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2008-04-25 05:55:19 -06:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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2009-10-20 10:40:47 -06:00
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#include <plat/dma.h>
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#include <plat/mcbsp.h>
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2008-04-25 05:55:19 -06:00
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#include "omap-mcbsp.h"
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#include "omap-pcm.h"
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2008-11-12 08:05:51 -07:00
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#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
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2008-04-25 05:55:19 -06:00
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2010-02-22 05:21:12 -07:00
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#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
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xhandler_get, xhandler_put) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = omap_mcbsp_st_info_volsw, \
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.get = xhandler_get, .put = xhandler_put, \
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.private_value = (unsigned long) &(struct soc_mixer_control) \
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{.min = xmin, .max = xmax} }
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2008-04-25 05:55:19 -06:00
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struct omap_mcbsp_data {
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unsigned int bus_id;
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struct omap_mcbsp_reg_cfg regs;
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2008-10-20 06:29:59 -06:00
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unsigned int fmt;
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2008-04-25 05:55:19 -06:00
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/*
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* Flags indicating is the bus already activated and configured by
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* another substream
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*/
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int active;
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int configured;
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2009-11-09 12:02:15 -07:00
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unsigned int in_freq;
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int clk_div;
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2010-06-02 22:39:35 -06:00
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int wlen;
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2008-04-25 05:55:19 -06:00
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};
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static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
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/*
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* Stream DMA parameters. DMA request line and port address are set runtime
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* since they are different between OMAP1 and later OMAPs
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*/
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2008-10-09 06:57:21 -06:00
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static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
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2008-04-25 05:55:19 -06:00
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#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
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static const int omap1_dma_reqs[][2] = {
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{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
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{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
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{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
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};
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static const unsigned long omap1_mcbsp_port[][2] = {
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{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
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};
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#else
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static const int omap1_dma_reqs[][2] = {};
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static const unsigned long omap1_mcbsp_port[][2] = {};
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#endif
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2008-10-09 06:57:20 -06:00
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2010-02-12 13:26:48 -07:00
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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2008-10-09 06:57:20 -06:00
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static const int omap24xx_dma_reqs[][2] = {
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2008-04-25 05:55:19 -06:00
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{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
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{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
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2010-02-12 13:26:48 -07:00
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
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2008-10-09 06:57:20 -06:00
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{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
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{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
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{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
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#endif
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2008-04-25 05:55:19 -06:00
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};
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2008-10-09 06:57:20 -06:00
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#else
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static const int omap24xx_dma_reqs[][2] = {};
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#endif
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#if defined(CONFIG_ARCH_OMAP2420)
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2008-04-25 05:55:19 -06:00
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static const unsigned long omap2420_mcbsp_port[][2] = {
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{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
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{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
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OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
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};
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#else
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static const unsigned long omap2420_mcbsp_port[][2] = {};
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#endif
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2008-10-09 06:57:20 -06:00
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#if defined(CONFIG_ARCH_OMAP2430)
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static const unsigned long omap2430_mcbsp_port[][2] = {
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{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
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OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
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OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
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OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
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};
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#else
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static const unsigned long omap2430_mcbsp_port[][2] = {};
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#endif
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2010-02-12 13:26:48 -07:00
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#if defined(CONFIG_ARCH_OMAP3)
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2008-10-09 06:57:20 -06:00
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static const unsigned long omap34xx_mcbsp_port[][2] = {
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{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
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{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
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OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
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};
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#else
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static const unsigned long omap34xx_mcbsp_port[][2] = {};
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#endif
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2009-08-20 07:18:25 -06:00
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static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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2010-03-17 14:15:21 -06:00
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
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2010-07-29 00:51:27 -06:00
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struct omap_pcm_dma_data *dma_data;
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2009-08-20 07:18:26 -06:00
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int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
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2010-06-02 22:39:35 -06:00
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int words;
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2009-08-20 07:18:26 -06:00
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2010-03-17 14:15:21 -06:00
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dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
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2010-07-29 00:51:27 -06:00
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2009-08-20 07:18:26 -06:00
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/* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
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if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
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2010-07-29 00:51:27 -06:00
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/*
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* Configure McBSP threshold based on either:
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* packet_size, when the sDMA is in packet mode, or
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* based on the period size.
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*/
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if (dma_data->packet_size)
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words = dma_data->packet_size;
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else
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words = snd_pcm_lib_period_bytes(substream) /
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2010-06-02 22:39:35 -06:00
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(mcbsp_data->wlen / 8);
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2009-08-20 07:18:26 -06:00
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else
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2010-06-02 22:39:35 -06:00
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words = 1;
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2009-08-20 07:18:25 -06:00
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/* Configure McBSP internal buffer usage */
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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2010-06-02 22:39:35 -06:00
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omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
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2009-08-20 07:18:25 -06:00
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else
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2010-06-02 22:39:35 -06:00
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omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
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2009-08-20 07:18:25 -06:00
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}
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2010-06-02 22:39:36 -06:00
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static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct snd_interval *buffer_size = hw_param_interval(params,
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SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
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struct snd_interval *channels = hw_param_interval(params,
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SNDRV_PCM_HW_PARAM_CHANNELS);
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struct omap_mcbsp_data *mcbsp_data = rule->private;
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struct snd_interval frames;
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int size;
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snd_interval_any(&frames);
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size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
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frames.min = size / channels->min;
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frames.integer = 1;
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return snd_interval_refine(buffer_size, &frames);
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}
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2008-11-18 15:11:38 -07:00
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static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
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2010-03-17 14:15:21 -06:00
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struct snd_soc_dai *cpu_dai)
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2008-04-25 05:55:19 -06:00
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{
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2010-03-17 14:15:21 -06:00
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struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
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2009-08-20 07:18:25 -06:00
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int bus_id = mcbsp_data->bus_id;
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2008-04-25 05:55:19 -06:00
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int err = 0;
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2009-08-20 07:18:25 -06:00
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if (!cpu_dai->active)
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err = omap_mcbsp_request(bus_id);
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2010-06-02 22:39:36 -06:00
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/*
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* OMAP3 McBSP FIFO is word structured.
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* McBSP2 has 1024 + 256 = 1280 word long buffer,
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* McBSP1,3,4,5 has 128 word long buffer
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* This means that the size of the FIFO depends on the sample format.
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* For example on McBSP3:
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* 16bit samples: size is 128 * 2 = 256 bytes
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* 32bit samples: size is 128 * 4 = 512 bytes
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* It is simpler to place constraint for buffer and period based on
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* channels.
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* McBSP3 as example again (16 or 32 bit samples):
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* 1 channel (mono): size is 128 frames (128 words)
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* 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
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* 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
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*/
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2009-08-20 07:18:25 -06:00
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if (cpu_is_omap343x()) {
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2009-03-27 07:32:01 -06:00
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/*
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2010-07-29 00:51:28 -06:00
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* Rule for the buffer size. We should not allow
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2010-06-02 22:39:36 -06:00
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* smaller buffer than the FIFO size to avoid underruns
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*/
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snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_CHANNELS,
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omap_mcbsp_hwrule_min_buffersize,
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mcbsp_data,
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SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
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2009-08-20 07:18:25 -06:00
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2010-07-29 00:51:28 -06:00
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/* Make sure, that the period size is always even */
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
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2009-03-27 07:32:01 -06:00
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}
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2008-04-25 05:55:19 -06:00
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return err;
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}
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2008-11-18 15:11:38 -07:00
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static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
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2010-03-17 14:15:21 -06:00
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struct snd_soc_dai *cpu_dai)
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2008-04-25 05:55:19 -06:00
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{
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2010-03-17 14:15:21 -06:00
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struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
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2008-04-25 05:55:19 -06:00
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if (!cpu_dai->active) {
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omap_mcbsp_free(mcbsp_data->bus_id);
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mcbsp_data->configured = 0;
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}
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}
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2008-11-18 15:11:38 -07:00
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static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
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2010-03-17 14:15:21 -06:00
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struct snd_soc_dai *cpu_dai)
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2008-04-25 05:55:19 -06:00
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{
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2010-03-17 14:15:21 -06:00
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struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
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2009-08-07 00:59:47 -06:00
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int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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2008-04-25 05:55:19 -06:00
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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2009-08-07 00:59:47 -06:00
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mcbsp_data->active++;
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omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
|
2008-04-25 05:55:19 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
2009-08-07 00:59:47 -06:00
|
|
|
omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
|
|
|
|
mcbsp_data->active--;
|
2008-04-25 05:55:19 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-03-03 06:08:09 -07:00
|
|
|
static snd_pcm_sframes_t omap_mcbsp_dai_delay(
|
|
|
|
struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
2010-03-17 14:15:21 -06:00
|
|
|
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
|
|
|
struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
|
2010-03-03 06:08:09 -07:00
|
|
|
u16 fifo_use;
|
|
|
|
snd_pcm_sframes_t delay;
|
|
|
|
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
|
|
|
|
else
|
|
|
|
fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Divide the used locations with the channel count to get the
|
|
|
|
* FIFO usage in samples (don't care about partial samples in the
|
|
|
|
* buffer).
|
|
|
|
*/
|
|
|
|
delay = fifo_use / substream->runtime->channels;
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2008-04-25 05:55:19 -06:00
|
|
|
static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
|
2008-11-18 15:11:38 -07:00
|
|
|
struct snd_pcm_hw_params *params,
|
2010-03-17 14:15:21 -06:00
|
|
|
struct snd_soc_dai *cpu_dai)
|
2008-04-25 05:55:19 -06:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
|
2008-04-25 05:55:19 -06:00
|
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
|
2010-07-29 00:51:26 -06:00
|
|
|
struct omap_pcm_dma_data *dma_data;
|
|
|
|
int dma, bus_id = mcbsp_data->bus_id;
|
2009-08-20 07:18:25 -06:00
|
|
|
int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
|
2010-07-29 00:51:27 -06:00
|
|
|
int pkt_size = 0;
|
2008-04-25 05:55:19 -06:00
|
|
|
unsigned long port;
|
2009-11-09 12:02:15 -07:00
|
|
|
unsigned int format, div, framesize, master;
|
2008-04-25 05:55:19 -06:00
|
|
|
|
2010-07-29 00:51:26 -06:00
|
|
|
dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
|
2008-04-25 05:55:19 -06:00
|
|
|
if (cpu_class_is_omap1()) {
|
|
|
|
dma = omap1_dma_reqs[bus_id][substream->stream];
|
|
|
|
port = omap1_mcbsp_port[bus_id][substream->stream];
|
|
|
|
} else if (cpu_is_omap2420()) {
|
2008-10-09 06:57:20 -06:00
|
|
|
dma = omap24xx_dma_reqs[bus_id][substream->stream];
|
2008-04-25 05:55:19 -06:00
|
|
|
port = omap2420_mcbsp_port[bus_id][substream->stream];
|
2008-10-09 06:57:20 -06:00
|
|
|
} else if (cpu_is_omap2430()) {
|
|
|
|
dma = omap24xx_dma_reqs[bus_id][substream->stream];
|
|
|
|
port = omap2430_mcbsp_port[bus_id][substream->stream];
|
|
|
|
} else if (cpu_is_omap343x()) {
|
|
|
|
dma = omap24xx_dma_reqs[bus_id][substream->stream];
|
|
|
|
port = omap34xx_mcbsp_port[bus_id][substream->stream];
|
2008-04-25 05:55:19 -06:00
|
|
|
} else {
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2010-05-13 09:48:16 -06:00
|
|
|
switch (params_format(params)) {
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
2010-07-29 00:51:26 -06:00
|
|
|
dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
|
2010-07-29 00:51:27 -06:00
|
|
|
wlen = 16;
|
2010-05-13 09:48:16 -06:00
|
|
|
break;
|
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
2010-07-29 00:51:26 -06:00
|
|
|
dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
|
2010-07-29 00:51:27 -06:00
|
|
|
wlen = 32;
|
2010-05-13 09:48:16 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2010-07-29 00:51:25 -06:00
|
|
|
if (cpu_is_omap343x()) {
|
|
|
|
dma_data->set_threshold = omap_mcbsp_set_threshold;
|
|
|
|
/* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
|
|
|
|
if (omap_mcbsp_get_dma_op_mode(bus_id) ==
|
2010-07-29 00:51:27 -06:00
|
|
|
MCBSP_DMA_MODE_THRESHOLD) {
|
|
|
|
int period_words, max_thrsh;
|
|
|
|
|
|
|
|
period_words = params_period_bytes(params) / (wlen / 8);
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
max_thrsh = omap_mcbsp_get_max_tx_threshold(
|
|
|
|
mcbsp_data->bus_id);
|
|
|
|
else
|
|
|
|
max_thrsh = omap_mcbsp_get_max_rx_threshold(
|
|
|
|
mcbsp_data->bus_id);
|
|
|
|
/*
|
|
|
|
* If the period contains less or equal number of words,
|
|
|
|
* we are using the original threshold mode setup:
|
|
|
|
* McBSP threshold = sDMA frame size = period_size
|
|
|
|
* Otherwise we switch to sDMA packet mode:
|
|
|
|
* McBSP threshold = sDMA packet size
|
|
|
|
* sDMA frame size = period size
|
|
|
|
*/
|
|
|
|
if (period_words > max_thrsh) {
|
|
|
|
int divider = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Look for the biggest threshold value, which
|
|
|
|
* divides the period size evenly.
|
|
|
|
*/
|
|
|
|
divider = period_words / max_thrsh;
|
|
|
|
if (period_words % max_thrsh)
|
|
|
|
divider++;
|
|
|
|
while (period_words % divider &&
|
|
|
|
divider < period_words)
|
|
|
|
divider++;
|
|
|
|
if (divider == period_words)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pkt_size = period_words / divider;
|
|
|
|
sync_mode = OMAP_DMA_SYNC_PACKET;
|
|
|
|
} else {
|
|
|
|
sync_mode = OMAP_DMA_SYNC_FRAME;
|
|
|
|
}
|
|
|
|
}
|
2010-07-29 00:51:25 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
|
|
|
|
dma_data->dma_req = dma;
|
|
|
|
dma_data->port_addr = port;
|
|
|
|
dma_data->sync_mode = sync_mode;
|
2010-07-29 00:51:27 -06:00
|
|
|
dma_data->packet_size = pkt_size;
|
2010-03-19 08:52:55 -06:00
|
|
|
|
2010-07-29 00:51:26 -06:00
|
|
|
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
|
2008-04-25 05:55:19 -06:00
|
|
|
|
|
|
|
if (mcbsp_data->configured) {
|
|
|
|
/* McBSP already configured by another stream */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-15 06:38:55 -06:00
|
|
|
format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
|
|
|
|
wpf = channels = params_channels(params);
|
2010-03-19 04:27:31 -06:00
|
|
|
if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
|
|
|
|
format == SND_SOC_DAIFMT_LEFT_J)) {
|
2009-11-09 12:02:15 -07:00
|
|
|
/* Use dual-phase frames */
|
|
|
|
regs->rcr2 |= RPHASE;
|
|
|
|
regs->xcr2 |= XPHASE;
|
|
|
|
/* Set 1 word per (McBSP) frame for phase1 and phase2 */
|
|
|
|
wpf--;
|
|
|
|
regs->rcr2 |= RFRLEN2(wpf - 1);
|
|
|
|
regs->xcr2 |= XFRLEN2(wpf - 1);
|
2008-04-25 05:55:19 -06:00
|
|
|
}
|
|
|
|
|
2009-11-09 12:02:15 -07:00
|
|
|
regs->rcr1 |= RFRLEN1(wpf - 1);
|
|
|
|
regs->xcr1 |= XFRLEN1(wpf - 1);
|
|
|
|
|
2008-04-25 05:55:19 -06:00
|
|
|
switch (params_format(params)) {
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
|
|
/* Set word lengths */
|
|
|
|
regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
|
|
|
|
regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
|
|
|
|
regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
|
|
|
|
regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
|
|
|
|
break;
|
2010-05-13 09:48:16 -06:00
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
|
|
/* Set word lengths */
|
|
|
|
regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
|
|
|
|
regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
|
|
|
|
regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
|
|
|
|
regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
|
|
|
|
break;
|
2008-04-25 05:55:19 -06:00
|
|
|
default:
|
|
|
|
/* Unsupported PCM format */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-11-09 12:02:15 -07:00
|
|
|
/* In McBSP master modes, FRAME (i.e. sample rate) is generated
|
|
|
|
* by _counting_ BCLKs. Calculate frame size in BCLKs */
|
|
|
|
master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
|
|
|
|
if (master == SND_SOC_DAIFMT_CBS_CFS) {
|
|
|
|
div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
|
|
|
|
framesize = (mcbsp_data->in_freq / div) / params_rate(params);
|
|
|
|
|
|
|
|
if (framesize < wlen * channels) {
|
|
|
|
printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
|
|
|
|
"channels\n", __func__);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
framesize = wlen * channels;
|
|
|
|
|
2008-10-20 06:29:59 -06:00
|
|
|
/* Set FS period and length in terms of bit clock periods */
|
2009-04-15 06:38:55 -06:00
|
|
|
switch (format) {
|
2008-10-20 06:29:59 -06:00
|
|
|
case SND_SOC_DAIFMT_I2S:
|
2010-03-19 04:27:31 -06:00
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
2009-11-09 12:02:15 -07:00
|
|
|
regs->srgr2 |= FPER(framesize - 1);
|
|
|
|
regs->srgr1 |= FWID((framesize >> 1) - 1);
|
2008-10-20 06:29:59 -06:00
|
|
|
break;
|
2009-04-15 06:38:56 -06:00
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
2008-12-22 01:21:36 -07:00
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
2009-11-09 12:02:15 -07:00
|
|
|
regs->srgr2 |= FPER(framesize - 1);
|
2009-04-15 04:48:16 -06:00
|
|
|
regs->srgr1 |= FWID(0);
|
2008-10-20 06:29:59 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-04-25 05:55:19 -06:00
|
|
|
omap_mcbsp_config(bus_id, &mcbsp_data->regs);
|
2010-06-02 22:39:35 -06:00
|
|
|
mcbsp_data->wlen = wlen;
|
2008-04-25 05:55:19 -06:00
|
|
|
mcbsp_data->configured = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This must be called before _set_clkdiv and _set_sysclk since McBSP register
|
|
|
|
* cache is initialized here
|
|
|
|
*/
|
2008-07-07 09:08:07 -06:00
|
|
|
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
|
2008-04-25 05:55:19 -06:00
|
|
|
unsigned int fmt)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
|
2008-04-25 05:55:19 -06:00
|
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
|
2009-04-15 04:48:16 -06:00
|
|
|
unsigned int temp_fmt = fmt;
|
2008-04-25 05:55:19 -06:00
|
|
|
|
|
|
|
if (mcbsp_data->configured)
|
|
|
|
return 0;
|
|
|
|
|
2008-10-20 06:29:59 -06:00
|
|
|
mcbsp_data->fmt = fmt;
|
2008-04-25 05:55:19 -06:00
|
|
|
memset(regs, 0, sizeof(*regs));
|
|
|
|
/* Generic McBSP register settings */
|
|
|
|
regs->spcr2 |= XINTM(3) | FREE;
|
|
|
|
regs->spcr1 |= RINTM(3);
|
2009-08-20 07:18:23 -06:00
|
|
|
/* RFIG and XFIG are not defined in 34xx */
|
|
|
|
if (!cpu_is_omap34xx()) {
|
|
|
|
regs->rcr2 |= RFIG;
|
|
|
|
regs->xcr2 |= XFIG;
|
|
|
|
}
|
2009-01-29 04:29:46 -07:00
|
|
|
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
|
2009-08-23 03:24:26 -06:00
|
|
|
regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
|
|
|
|
regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
|
2009-01-29 04:29:46 -07:00
|
|
|
}
|
2008-04-25 05:55:19 -06:00
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
/* 1-bit data delay */
|
|
|
|
regs->rcr2 |= RDATDLY(1);
|
|
|
|
regs->xcr2 |= XDATDLY(1);
|
|
|
|
break;
|
2010-03-19 04:27:31 -06:00
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
/* 0-bit data delay */
|
|
|
|
regs->rcr2 |= RDATDLY(0);
|
|
|
|
regs->xcr2 |= XDATDLY(0);
|
|
|
|
regs->spcr1 |= RJUST(2);
|
|
|
|
/* Invert FS polarity configuration */
|
|
|
|
temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
|
|
|
|
break;
|
2009-04-15 06:38:56 -06:00
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
/* 1-bit data delay */
|
|
|
|
regs->rcr2 |= RDATDLY(1);
|
|
|
|
regs->xcr2 |= XDATDLY(1);
|
|
|
|
/* Invert FS polarity configuration */
|
|
|
|
temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
|
|
|
|
break;
|
2008-12-22 01:21:36 -07:00
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
2008-10-02 03:37:06 -06:00
|
|
|
/* 0-bit data delay */
|
|
|
|
regs->rcr2 |= RDATDLY(0);
|
|
|
|
regs->xcr2 |= XDATDLY(0);
|
2009-04-15 04:48:16 -06:00
|
|
|
/* Invert FS polarity configuration */
|
|
|
|
temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
|
2008-10-02 03:37:06 -06:00
|
|
|
break;
|
2008-04-25 05:55:19 -06:00
|
|
|
default:
|
|
|
|
/* Unsupported data format */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
/* McBSP master. Set FS and bit clocks as outputs */
|
|
|
|
regs->pcr0 |= FSXM | FSRM |
|
|
|
|
CLKXM | CLKRM;
|
|
|
|
/* Sample rate generator drives the FS */
|
|
|
|
regs->srgr2 |= FSGM;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
/* McBSP slave */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Unsupported master/slave configuration */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set bit clock (CLKX/CLKR) and FS polarities */
|
2009-04-15 04:48:16 -06:00
|
|
|
switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
|
2008-04-25 05:55:19 -06:00
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
/*
|
|
|
|
* Normal BCLK + FS.
|
|
|
|
* FS active low. TX data driven on falling edge of bit clock
|
|
|
|
* and RX data sampled on rising edge of bit clock.
|
|
|
|
*/
|
|
|
|
regs->pcr0 |= FSXP | FSRP |
|
|
|
|
CLKXP | CLKRP;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
regs->pcr0 |= CLKXP | CLKRP;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
regs->pcr0 |= FSXP | FSRP;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-07 09:08:07 -06:00
|
|
|
static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
|
2008-04-25 05:55:19 -06:00
|
|
|
int div_id, int div)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
|
2008-04-25 05:55:19 -06:00
|
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
|
|
|
|
|
|
|
|
if (div_id != OMAP_MCBSP_CLKGDV)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2009-11-09 12:02:15 -07:00
|
|
|
mcbsp_data->clk_div = div;
|
2008-04-25 05:55:19 -06:00
|
|
|
regs->srgr1 |= CLKGDV(div - 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-07 09:08:07 -06:00
|
|
|
static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
|
2008-04-25 05:55:19 -06:00
|
|
|
int clk_id, unsigned int freq,
|
|
|
|
int dir)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
|
2008-04-25 05:55:19 -06:00
|
|
|
struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
|
|
|
|
int err = 0;
|
|
|
|
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
/* The McBSP signal muxing functions are only available on McBSP1 */
|
|
|
|
if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR ||
|
|
|
|
clk_id == OMAP_MCBSP_CLKR_SRC_CLKX ||
|
|
|
|
clk_id == OMAP_MCBSP_FSR_SRC_FSR ||
|
|
|
|
clk_id == OMAP_MCBSP_FSR_SRC_FSX)
|
|
|
|
if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-11-09 12:02:15 -07:00
|
|
|
mcbsp_data->in_freq = freq;
|
|
|
|
|
2008-04-25 05:55:19 -06:00
|
|
|
switch (clk_id) {
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLK:
|
|
|
|
regs->srgr2 |= CLKSM;
|
|
|
|
break;
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
|
2010-10-08 11:40:19 -06:00
|
|
|
if (cpu_class_is_omap1()) {
|
|
|
|
err = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
|
|
|
|
MCBSP_CLKS_PRCM_SRC);
|
|
|
|
break;
|
2008-04-25 05:55:19 -06:00
|
|
|
case OMAP_MCBSP_SYSCLK_CLKS_EXT:
|
2010-10-08 11:40:19 -06:00
|
|
|
if (cpu_class_is_omap1()) {
|
|
|
|
err = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
|
|
|
|
MCBSP_CLKS_PAD_SRC);
|
2008-04-25 05:55:19 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLKX_EXT:
|
|
|
|
regs->srgr2 |= CLKSM;
|
|
|
|
case OMAP_MCBSP_SYSCLK_CLKR_EXT:
|
|
|
|
regs->pcr0 |= SCLKME;
|
|
|
|
break;
|
2009-08-28 06:35:35 -06:00
|
|
|
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
|
2009-08-28 06:35:35 -06:00
|
|
|
case OMAP_MCBSP_CLKR_SRC_CLKR:
|
2010-11-02 08:50:32 -06:00
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
break;
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR);
|
|
|
|
break;
|
2009-08-28 06:35:35 -06:00
|
|
|
case OMAP_MCBSP_CLKR_SRC_CLKX:
|
2010-11-02 08:50:32 -06:00
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
break;
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX);
|
|
|
|
break;
|
2009-08-28 06:35:35 -06:00
|
|
|
case OMAP_MCBSP_FSR_SRC_FSR:
|
2010-11-02 08:50:32 -06:00
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
break;
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR);
|
|
|
|
break;
|
2009-08-28 06:35:35 -06:00
|
|
|
case OMAP_MCBSP_FSR_SRC_FSX:
|
2010-11-02 08:50:32 -06:00
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
break;
|
OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via
direct System Control Module writes on OMAP2+. This required the
omap_ctrl_{read,write}l() functions to be exported, which is against
policy: the only code that should call those functions directly is
OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no
longer exported, so the driver no longer builds as a module.
Fix the pinmuxing part of the problem by removing calls to
omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and
implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c.
Due to the unfortunate way that McBSP support is implemented in ASoC
and the OMAP tree, these symbols must be exported for use by
sound/soc/omap/omap-mcbsp.c.
Going forward, the McBSP device driver should be moved from
arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver
should be implemented as a platform_driver as many other ASoC CPU DAI
drivers are. These two steps should resolve many of the layering
problems, which will rapidly reappear during a McBSP hwmod/PM runtime
conversion.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-10-08 11:40:19 -06:00
|
|
|
omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX);
|
2009-08-28 06:35:35 -06:00
|
|
|
break;
|
2008-04-25 05:55:19 -06:00
|
|
|
default:
|
|
|
|
err = -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_ops mcbsp_dai_ops = {
|
2009-03-02 18:41:00 -07:00
|
|
|
.startup = omap_mcbsp_dai_startup,
|
|
|
|
.shutdown = omap_mcbsp_dai_shutdown,
|
|
|
|
.trigger = omap_mcbsp_dai_trigger,
|
2010-03-03 06:08:09 -07:00
|
|
|
.delay = omap_mcbsp_dai_delay,
|
2009-03-02 18:41:00 -07:00
|
|
|
.hw_params = omap_mcbsp_dai_hw_params,
|
|
|
|
.set_fmt = omap_mcbsp_dai_set_dai_fmt,
|
|
|
|
.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
|
|
|
|
.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
|
|
|
|
};
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static int mcbsp_dai_probe(struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
mcbsp_data[dai->id].bus_id = dai->id;
|
|
|
|
snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
|
|
|
|
return 0;
|
2008-10-09 06:57:22 -06:00
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_driver omap_mcbsp_dai =
|
|
|
|
{
|
|
|
|
.probe = mcbsp_dai_probe,
|
|
|
|
.playback = {
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 16,
|
|
|
|
.rates = OMAP_MCBSP_RATES,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 16,
|
|
|
|
.rates = OMAP_MCBSP_RATES,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
|
},
|
|
|
|
.ops = &mcbsp_dai_ops,
|
2008-04-25 05:55:19 -06:00
|
|
|
};
|
2008-10-09 06:57:22 -06:00
|
|
|
|
2010-09-07 21:23:43 -06:00
|
|
|
static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
|
2010-02-22 05:21:12 -07:00
|
|
|
struct snd_ctl_elem_info *uinfo)
|
|
|
|
{
|
|
|
|
struct soc_mixer_control *mc =
|
|
|
|
(struct soc_mixer_control *)kcontrol->private_value;
|
|
|
|
int max = mc->max;
|
|
|
|
int min = mc->min;
|
|
|
|
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
|
|
|
uinfo->count = 1;
|
|
|
|
uinfo->value.integer.min = min;
|
|
|
|
uinfo->value.integer.max = max;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
|
|
|
|
static int \
|
|
|
|
omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
|
|
|
|
struct snd_ctl_elem_value *uc) \
|
|
|
|
{ \
|
|
|
|
struct soc_mixer_control *mc = \
|
|
|
|
(struct soc_mixer_control *)kc->private_value; \
|
|
|
|
int max = mc->max; \
|
|
|
|
int min = mc->min; \
|
|
|
|
int val = uc->value.integer.value[0]; \
|
|
|
|
\
|
|
|
|
if (val < min || val > max) \
|
|
|
|
return -EINVAL; \
|
|
|
|
\
|
|
|
|
/* OMAP McBSP implementation uses index values 0..4 */ \
|
|
|
|
return omap_st_set_chgain((id)-1, channel, val); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
|
|
|
|
static int \
|
|
|
|
omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
|
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struct snd_ctl_elem_value *uc) \
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{ \
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s16 chgain; \
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\
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if (omap_st_get_chgain((id)-1, channel, &chgain)) \
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return -EAGAIN; \
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\
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uc->value.integer.value[0] = chgain; \
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return 0; \
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}
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OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
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OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
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OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
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OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
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OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
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OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
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OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
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OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
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static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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|
|
{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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u8 value = ucontrol->value.integer.value[0];
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if (value == omap_st_is_enabled(mc->reg))
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return 0;
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if (value)
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omap_st_enable(mc->reg);
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else
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omap_st_disable(mc->reg);
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return 1;
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}
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static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
|
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|
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{
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|
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
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return 0;
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}
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static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
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SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
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omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
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OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
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|
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-32768, 32767,
|
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omap_mcbsp2_get_st_ch0_volume,
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omap_mcbsp2_set_st_ch0_volume),
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|
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OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
|
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|
|
-32768, 32767,
|
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|
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omap_mcbsp2_get_st_ch1_volume,
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|
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omap_mcbsp2_set_st_ch1_volume),
|
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|
|
};
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
|
|
|
|
SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
|
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|
|
omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
|
|
|
|
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
|
|
|
|
-32768, 32767,
|
|
|
|
omap_mcbsp3_get_st_ch0_volume,
|
|
|
|
omap_mcbsp3_set_st_ch0_volume),
|
|
|
|
OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
|
|
|
|
-32768, 32767,
|
|
|
|
omap_mcbsp3_get_st_ch1_volume,
|
|
|
|
omap_mcbsp3_set_st_ch1_volume),
|
|
|
|
};
|
|
|
|
|
|
|
|
int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
|
|
|
|
{
|
|
|
|
if (!cpu_is_omap34xx())
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
switch (mcbsp_id) {
|
|
|
|
case 1: /* McBSP 2 */
|
|
|
|
return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
|
|
|
|
ARRAY_SIZE(omap_mcbsp2_st_controls));
|
|
|
|
case 2: /* McBSP 3 */
|
|
|
|
return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
|
|
|
|
ARRAY_SIZE(omap_mcbsp3_st_controls));
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
snd_soc_unregister_dai(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver asoc_mcbsp_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "omap-mcbsp-dai",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
|
|
|
|
.probe = asoc_mcbsp_probe,
|
|
|
|
.remove = __devexit_p(asoc_mcbsp_remove),
|
|
|
|
};
|
|
|
|
|
2008-12-09 23:59:33 -07:00
|
|
|
static int __init snd_omap_mcbsp_init(void)
|
2008-12-03 12:26:35 -07:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
return platform_driver_register(&asoc_mcbsp_driver);
|
2008-12-03 12:26:35 -07:00
|
|
|
}
|
2008-12-09 23:59:33 -07:00
|
|
|
module_init(snd_omap_mcbsp_init);
|
2008-12-03 12:26:35 -07:00
|
|
|
|
2008-12-09 23:59:33 -07:00
|
|
|
static void __exit snd_omap_mcbsp_exit(void)
|
2008-12-03 12:26:35 -07:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
platform_driver_unregister(&asoc_mcbsp_driver);
|
2008-12-03 12:26:35 -07:00
|
|
|
}
|
2008-12-09 23:59:33 -07:00
|
|
|
module_exit(snd_omap_mcbsp_exit);
|
2008-12-03 12:26:35 -07:00
|
|
|
|
2009-04-17 05:42:26 -06:00
|
|
|
MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
|
2008-04-25 05:55:19 -06:00
|
|
|
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
|
|
|
|
MODULE_LICENSE("GPL");
|