2005-04-16 16:20:36 -06:00
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/*
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* pci.h
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*
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* PCI defines and function prototypes
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*/
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#ifndef LINUX_PCI_H
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#define LINUX_PCI_H
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2008-06-10 15:28:50 -06:00
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#include <linux/pci_regs.h> /* The pci register defines */
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2005-04-16 16:20:36 -06:00
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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* in a single byte as follows:
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*
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* 7:3 = slot
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* 2:0 = function
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*/
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2008-01-30 16:21:33 -07:00
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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2005-04-16 16:20:36 -06:00
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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/* Ioctls for /proc/bus/pci/X/Y nodes. */
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#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
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#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
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#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
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#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
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#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
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#ifdef __KERNEL__
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2006-04-28 18:46:02 -06:00
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#include <linux/mod_devicetable.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/types.h>
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2008-04-29 14:38:48 -06:00
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#include <linux/init.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/ioport.h>
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#include <linux/list.h>
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2006-08-14 23:43:17 -06:00
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#include <linux/compiler.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/errno.h>
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2008-06-10 15:28:50 -06:00
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#include <linux/kobject.h>
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PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
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#include <asm/atomic.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/device.h>
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2008-10-21 20:39:55 -06:00
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#include <linux/io.h>
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2009-03-19 21:25:16 -06:00
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#include <linux/irqreturn.h>
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2005-04-16 16:20:36 -06:00
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2006-12-19 14:12:07 -07:00
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/* Include the ID list */
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#include <linux/pci_ids.h>
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2008-06-10 15:28:50 -06:00
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/* pci_slot represents a physical slot */
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struct pci_slot {
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struct pci_bus *bus; /* The bus this slot is on */
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struct list_head list; /* node in list of slots on this bus */
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struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
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unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
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struct kobject kobj;
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};
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2008-10-20 17:41:07 -06:00
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static inline const char *pci_slot_name(const struct pci_slot *slot)
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{
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return kobject_name(&slot->kobj);
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}
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2005-04-16 16:20:36 -06:00
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/* File state for mmap()s on /proc/bus/pci/X/Y */
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enum pci_mmap_state {
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pci_mmap_io,
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pci_mmap_mem
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};
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/* This defines the direction arg to the DMA mapping routines. */
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#define PCI_DMA_BIDIRECTIONAL 0
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#define PCI_DMA_TODEVICE 1
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#define PCI_DMA_FROMDEVICE 2
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#define PCI_DMA_NONE 3
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2008-11-21 11:39:32 -07:00
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/*
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* For PCI devices, the region numbers are assigned this way:
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*/
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enum {
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/* #0-5: standard PCI resources */
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PCI_STD_RESOURCES,
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PCI_STD_RESOURCE_END = 5,
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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2009-03-19 21:25:11 -06:00
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/* device specific resources */
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#ifdef CONFIG_PCI_IOV
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PCI_IOV_RESOURCES,
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PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
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#endif
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2008-11-21 11:39:32 -07:00
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/* resources assigned to buses behind the bridge */
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#define PCI_BRIDGE_RESOURCE_NUM 4
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PCI_BRIDGE_RESOURCES,
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PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
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PCI_BRIDGE_RESOURCE_NUM - 1,
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/* total resources associated with a PCI device */
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PCI_NUM_RESOURCES,
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/* preserve this for compatibility */
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DEVICE_COUNT_RESOURCE
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};
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2005-04-16 16:20:36 -06:00
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typedef int __bitwise pci_power_t;
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2005-07-28 12:37:33 -06:00
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#define PCI_D0 ((pci_power_t __force) 0)
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#define PCI_D1 ((pci_power_t __force) 1)
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#define PCI_D2 ((pci_power_t __force) 2)
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2005-04-16 16:20:36 -06:00
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#define PCI_D3hot ((pci_power_t __force) 3)
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#define PCI_D3cold ((pci_power_t __force) 4)
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2005-08-17 16:32:19 -06:00
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#define PCI_UNKNOWN ((pci_power_t __force) 5)
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2005-04-16 16:25:24 -06:00
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#define PCI_POWER_ERROR ((pci_power_t __force) -1)
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2005-04-16 16:20:36 -06:00
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2009-04-27 11:33:16 -06:00
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/* Remember to update this when the list above changes! */
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extern const char *pci_power_names[];
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static inline const char *pci_power_name(pci_power_t state)
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{
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return pci_power_names[1 + (int) state];
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}
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2009-01-16 13:54:43 -07:00
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#define PCI_PM_D2_DELAY 200
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#define PCI_PM_D3_WAIT 10
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#define PCI_PM_BUS_WAIT 50
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2005-11-16 16:10:41 -07:00
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/** The pci_channel state describes connectivity between the CPU and
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* the pci device. If some PCI bus between here and the pci device
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* has crashed or locked up, this info is reflected here.
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*/
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typedef unsigned int __bitwise pci_channel_state_t;
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enum pci_channel_state {
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/* I/O channel is in normal state */
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pci_channel_io_normal = (__force pci_channel_state_t) 1,
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/* I/O to channel is blocked */
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pci_channel_io_frozen = (__force pci_channel_state_t) 2,
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/* PCI card is dead */
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pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
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};
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2007-04-06 15:39:36 -06:00
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typedef unsigned int __bitwise pcie_reset_state_t;
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enum pcie_reset_state {
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/* Reset is NOT asserted (Use to deassert reset) */
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pcie_deassert_reset = (__force pcie_reset_state_t) 1,
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/* Use #PERST to reset PCI-E device */
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pcie_warm_reset = (__force pcie_reset_state_t) 2,
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/* Use PCI-E Hot Reset to reset device */
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pcie_hot_reset = (__force pcie_reset_state_t) 3
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};
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2007-10-25 02:16:30 -06:00
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typedef unsigned short __bitwise pci_dev_flags_t;
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enum pci_dev_flags {
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/* INTX_DISABLE in PCI_COMMAND register disables MSI
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* generation too.
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*/
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PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
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2008-07-24 10:18:38 -06:00
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/* Device configuration is irrevocably lost if disabled into D3 */
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PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
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2007-10-25 02:16:30 -06:00
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};
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2008-06-11 08:35:17 -06:00
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enum pci_irq_reroute_variant {
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INTEL_IRQ_REROUTE_VARIANT = 1,
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MAX_IRQ_REROUTE_VARIANTS = 3
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};
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2006-02-14 09:52:22 -07:00
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typedef unsigned short __bitwise pci_bus_flags_t;
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enum pci_bus_flags {
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2007-05-15 05:59:13 -06:00
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PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
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PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
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2006-02-14 09:52:22 -07:00
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};
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2006-02-08 02:11:38 -07:00
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struct pci_cap_saved_state {
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struct hlist_node next;
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char cap_nr;
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u32 data[0];
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};
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PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-24 18:46:41 -07:00
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struct pcie_link_state;
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2008-04-28 13:30:35 -06:00
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struct pci_vpd;
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2009-03-19 21:25:11 -06:00
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struct pci_sriov;
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2009-05-17 23:51:32 -06:00
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struct pci_ats;
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2008-04-28 13:30:35 -06:00
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2005-04-16 16:20:36 -06:00
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/*
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* The pci_dev structure is used to describe PCI devices.
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*/
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struct pci_dev {
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struct list_head bus_list; /* node in per-bus list */
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struct pci_bus *bus; /* bus this device is on */
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struct pci_bus *subordinate; /* bus this device bridges to */
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void *sysdata; /* hook for sys-specific extension */
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struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
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2008-06-10 15:28:50 -06:00
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struct pci_slot *slot; /* Physical slot this device is in */
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2005-04-16 16:20:36 -06:00
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unsigned int devfn; /* encoded device & function index */
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unsigned short vendor;
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unsigned short device;
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unsigned short subsystem_vendor;
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unsigned short subsystem_device;
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unsigned int class; /* 3 bytes: (base,sub,prog-if) */
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2007-06-08 16:46:30 -06:00
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u8 revision; /* PCI revision, low byte of class word */
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2005-04-16 16:20:36 -06:00
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u8 hdr_type; /* PCI header type (`multi' flag masked out) */
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2009-11-04 20:05:11 -07:00
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u8 pcie_cap; /* PCI-E capability offset */
|
2007-10-21 17:41:46 -06:00
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u8 pcie_type; /* PCI-E device/port type */
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2005-04-16 16:20:36 -06:00
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u8 rom_base_reg; /* which config register controls the ROM */
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2005-11-02 17:24:32 -07:00
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u8 pin; /* which interrupt pin this device uses */
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2005-04-16 16:20:36 -06:00
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struct pci_driver *driver; /* which driver has allocated this device */
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u64 dma_mask; /* Mask of the bits of bus address this
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device implements. Normally this is
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0xffffffff. You only need to change
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this if your device has broken DMA
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or supports 64-bit transfers. */
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2008-02-04 23:27:55 -07:00
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struct device_dma_parameters dma_parms;
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2005-04-16 16:20:36 -06:00
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pci_power_t current_state; /* Current operating state. In ACPI-speak,
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this is D0-D3, D0 being fully functional,
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and D3 being off. */
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2008-07-06 19:36:24 -06:00
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int pm_cap; /* PM capability offset in the
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configuration space */
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unsigned int pme_support:5; /* Bitmask of states from which PME#
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can be generated */
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unsigned int d1_support:1; /* Low power state D1 is supported */
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unsigned int d2_support:1; /* Low power state D2 is supported */
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unsigned int no_d1d2:1; /* Only allow D0 and D3 */
|
2009-09-08 15:14:49 -06:00
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unsigned int wakeup_prepared:1;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-24 18:46:41 -07:00
|
|
|
#ifdef CONFIG_PCIEASPM
|
|
|
|
struct pcie_link_state *link_state; /* ASPM link state. */
|
|
|
|
#endif
|
|
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|
2005-11-16 16:10:41 -07:00
|
|
|
pci_channel_state_t error_state; /* current connectivity state */
|
2005-04-16 16:20:36 -06:00
|
|
|
struct device dev; /* Generic device interface */
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|
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|
int cfg_size; /* Size of configuration space */
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/*
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|
|
|
* Instead of touching interrupt line and base address registers
|
|
|
|
* directly, use the values stored here. They might be different!
|
|
|
|
*/
|
|
|
|
unsigned int irq;
|
|
|
|
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
|
|
|
|
|
|
|
|
/* These fields are used by common fixups */
|
|
|
|
unsigned int transparent:1; /* Transparent PCI bridge */
|
|
|
|
unsigned int multifunction:1;/* Part of multi-function device */
|
|
|
|
/* keep track of device state */
|
2008-02-14 15:56:56 -07:00
|
|
|
unsigned int is_added:1;
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned int is_busmaster:1; /* device is busmaster */
|
2005-08-16 16:15:58 -06:00
|
|
|
unsigned int no_msi:1; /* device may not use msi */
|
2005-09-27 02:21:55 -06:00
|
|
|
unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
|
2006-05-08 18:06:09 -06:00
|
|
|
unsigned int broken_parity_status:1; /* Device generates false positive parity */
|
2008-06-11 08:35:17 -06:00
|
|
|
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
|
2006-05-25 20:58:27 -06:00
|
|
|
unsigned int msi_enabled:1;
|
|
|
|
unsigned int msix_enabled:1;
|
2008-10-14 00:02:53 -06:00
|
|
|
unsigned int ari_enabled:1; /* ARI forwarding */
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
unsigned int is_managed:1;
|
2007-10-21 17:41:46 -06:00
|
|
|
unsigned int is_pcie:1;
|
2009-07-30 16:33:21 -06:00
|
|
|
unsigned int needs_freset:1; /* Dev requires fundamental reset */
|
2009-01-16 13:54:43 -07:00
|
|
|
unsigned int state_saved:1;
|
2009-03-19 21:25:11 -06:00
|
|
|
unsigned int is_physfn:1;
|
2009-03-19 21:25:15 -06:00
|
|
|
unsigned int is_virtfn:1;
|
2009-07-27 14:37:48 -06:00
|
|
|
unsigned int reset_fn:1;
|
2009-09-09 15:09:24 -06:00
|
|
|
unsigned int is_hotplug_bridge:1;
|
PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode
Feedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This
correctly handles PCI-X bridges, PCIe root ports and endpoints, and
prints debug messages when invalid/reserved types are found in the
HEST. PCI devices not in domain/segment 0 are not represented in
HEST, thus will be ignored.
Today, the PCIe Advanced Error Reporting (AER) driver attaches itself
to every PCIe root port for which BIOS reports it should, via ACPI
_OSC.
However, _OSC alone is insufficient for newer BIOSes. Part of ACPI
4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way
for OS and BIOS to handshake over which errors for which components
each will handle. One table in ACPI 4.0 is the Hardware Error Source
Table (HEST), where BIOS can define that errors for certain PCIe
devices (or all devices), should be handled by BIOS ("Firmware First
mode"), rather than be handled by the OS.
Dell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so
that it may manage such errors, log them to the System Event Log, and
possibly take other actions. The aer driver should honor this, and
not attach itself to devices noted as such.
Furthermore, Kenji Kaneshige reminded us to disallow changing the AER
registers when respecting Firmware First mode. Platform firmware is
expected to manage these, and if changes to them are allowed, it could
break that firmware's behavior.
The HEST parsing code may be replaced in the future by a more
feature-rich implementation. This patch provides the minimum needed
to prevent breakage until that implementation is available.
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Matt Domsch <Matt_Domsch@dell.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-11-02 10:51:24 -07:00
|
|
|
unsigned int aer_firmware_first:1;
|
2007-10-25 02:16:30 -06:00
|
|
|
pci_dev_flags_t dev_flags;
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
|
|
|
atomic_t enable_cnt; /* pci_enable_device has been called */
|
2005-08-16 16:15:58 -06:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
u32 saved_config_space[16]; /* config space saved at suspend time */
|
2006-02-08 02:11:38 -07:00
|
|
|
struct hlist_head saved_cap_space;
|
2005-04-16 16:20:36 -06:00
|
|
|
struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
|
|
|
|
int rom_attr_enabled; /* has display of the rom attribute been enabled? */
|
|
|
|
struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
|
2008-03-18 18:00:22 -06:00
|
|
|
struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
|
2007-01-28 12:42:52 -07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
2007-04-05 01:19:10 -06:00
|
|
|
struct list_head msi_list;
|
2007-01-28 12:42:52 -07:00
|
|
|
#endif
|
2008-03-05 09:52:39 -07:00
|
|
|
struct pci_vpd *vpd;
|
2009-03-19 21:25:11 -06:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
2009-03-19 21:25:15 -06:00
|
|
|
union {
|
|
|
|
struct pci_sriov *sriov; /* SR-IOV capability related */
|
|
|
|
struct pci_dev *physfn; /* the PF this VF is associated with */
|
|
|
|
};
|
2009-05-17 23:51:32 -06:00
|
|
|
struct pci_ats *ats; /* Address Translation Service */
|
2009-03-19 21:25:11 -06:00
|
|
|
#endif
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2007-04-05 01:19:08 -06:00
|
|
|
extern struct pci_dev *alloc_pci_dev(void);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
|
|
|
|
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
|
|
|
|
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
|
|
|
|
|
2006-12-12 15:55:59 -07:00
|
|
|
static inline int pci_channel_offline(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return (pdev->error_state != pci_channel_io_normal);
|
|
|
|
}
|
|
|
|
|
2006-02-08 02:11:38 -07:00
|
|
|
static inline struct pci_cap_saved_state *pci_find_saved_cap(
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev *pci_dev, char cap)
|
2006-02-08 02:11:38 -07:00
|
|
|
{
|
|
|
|
struct pci_cap_saved_state *tmp;
|
|
|
|
struct hlist_node *pos;
|
|
|
|
|
|
|
|
hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
|
|
|
|
if (tmp->cap_nr == cap)
|
|
|
|
return tmp;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
|
|
|
|
struct pci_cap_saved_state *new_cap)
|
|
|
|
{
|
|
|
|
hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifndef PCI_BUS_NUM_RESOURCES
|
2008-02-19 04:21:20 -07:00
|
|
|
#define PCI_BUS_NUM_RESOURCES 16
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
2005-07-28 12:37:33 -06:00
|
|
|
|
|
|
|
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
struct pci_bus {
|
|
|
|
struct list_head node; /* node in list of buses */
|
|
|
|
struct pci_bus *parent; /* parent bus this bridge is on */
|
|
|
|
struct list_head children; /* list of child buses */
|
|
|
|
struct list_head devices; /* list of devices on this bus */
|
|
|
|
struct pci_dev *self; /* bridge device as seen by parent */
|
2008-06-10 15:28:50 -06:00
|
|
|
struct list_head slots; /* list of slots on this bus */
|
2005-04-16 16:20:36 -06:00
|
|
|
struct resource *resource[PCI_BUS_NUM_RESOURCES];
|
|
|
|
/* address space routed to this bus */
|
|
|
|
|
|
|
|
struct pci_ops *ops; /* configuration access functions */
|
|
|
|
void *sysdata; /* hook for sys-specific extension */
|
|
|
|
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
|
|
|
|
|
|
|
|
unsigned char number; /* bus number */
|
|
|
|
unsigned char primary; /* number of primary bridge */
|
|
|
|
unsigned char secondary; /* number of secondary bridge */
|
|
|
|
unsigned char subordinate; /* max number of subordinate buses */
|
|
|
|
|
|
|
|
char name[48];
|
|
|
|
|
|
|
|
unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
|
2006-02-14 09:52:22 -07:00
|
|
|
pci_bus_flags_t bus_flags; /* Inherited by child busses */
|
2005-04-16 16:20:36 -06:00
|
|
|
struct device *bridge;
|
2007-05-22 20:47:54 -06:00
|
|
|
struct device dev;
|
2005-04-16 16:20:36 -06:00
|
|
|
struct bin_attribute *legacy_io; /* legacy I/O for this bus */
|
|
|
|
struct bin_attribute *legacy_mem; /* legacy mem */
|
2008-03-12 22:48:03 -06:00
|
|
|
unsigned int is_added:1;
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
|
2007-05-22 20:47:54 -06:00
|
|
|
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-03-20 14:55:55 -06:00
|
|
|
/*
|
|
|
|
* Returns true if the pci bus is root (behind host-pci bridge),
|
|
|
|
* false otherwise
|
|
|
|
*/
|
|
|
|
static inline bool pci_is_root_bus(struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
return !(pbus->parent);
|
|
|
|
}
|
|
|
|
|
2009-01-05 06:50:27 -07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
|
|
|
|
{
|
|
|
|
return pci_dev->msi_enabled || pci_dev->msix_enabled;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
* Error values that may be returned by PCI functions.
|
|
|
|
*/
|
|
|
|
#define PCIBIOS_SUCCESSFUL 0x00
|
|
|
|
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
|
|
|
#define PCIBIOS_BAD_VENDOR_ID 0x83
|
|
|
|
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
|
|
|
|
#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
|
|
|
|
#define PCIBIOS_SET_FAILED 0x88
|
|
|
|
#define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
|
|
|
|
|
|
|
/* Low-level architecture-dependent routines */
|
|
|
|
|
|
|
|
struct pci_ops {
|
|
|
|
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
|
|
|
|
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
|
|
|
|
};
|
|
|
|
|
2008-02-10 07:45:28 -07:00
|
|
|
/*
|
|
|
|
* ACPI needs to be able to access PCI config space before we've done a
|
|
|
|
* PCI bus scan and created pci_bus structures.
|
|
|
|
*/
|
|
|
|
extern int raw_pci_read(unsigned int domain, unsigned int bus,
|
|
|
|
unsigned int devfn, int reg, int len, u32 *val);
|
|
|
|
extern int raw_pci_write(unsigned int domain, unsigned int bus,
|
|
|
|
unsigned int devfn, int reg, int len, u32 val);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
struct pci_bus_region {
|
2007-12-09 23:32:15 -07:00
|
|
|
resource_size_t start;
|
|
|
|
resource_size_t end;
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
struct pci_dynids {
|
|
|
|
spinlock_t lock; /* protects list, index */
|
|
|
|
struct list_head list; /* for IDs added at runtime */
|
|
|
|
};
|
|
|
|
|
2005-11-16 16:10:41 -07:00
|
|
|
/* ---------------------------------------------------------------- */
|
|
|
|
/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
|
2007-07-10 05:35:05 -06:00
|
|
|
* a set of callbacks in struct pci_error_handlers, then that device driver
|
2005-11-16 16:10:41 -07:00
|
|
|
* will be notified of PCI bus errors, and will be driven to recovery
|
|
|
|
* when an error occurs.
|
|
|
|
*/
|
|
|
|
|
|
|
|
typedef unsigned int __bitwise pci_ers_result_t;
|
|
|
|
|
|
|
|
enum pci_ers_result {
|
|
|
|
/* no result/none/not supported in device driver */
|
|
|
|
PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
|
|
|
|
|
|
|
|
/* Device driver can recover without slot reset */
|
|
|
|
PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
|
|
|
|
|
|
|
|
/* Device driver wants slot to be reset. */
|
|
|
|
PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
|
|
|
|
|
|
|
|
/* Device has completely failed, is unrecoverable */
|
|
|
|
PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
|
|
|
|
|
|
|
|
/* Device driver is fully recovered and operational */
|
|
|
|
PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* PCI bus error event callbacks */
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_error_handlers {
|
2005-11-16 16:10:41 -07:00
|
|
|
/* PCI bus error detected on this device */
|
|
|
|
pci_ers_result_t (*error_detected)(struct pci_dev *dev,
|
2008-01-30 16:21:33 -07:00
|
|
|
enum pci_channel_state error);
|
2005-11-16 16:10:41 -07:00
|
|
|
|
|
|
|
/* MMIO has been re-enabled, but not DMA */
|
|
|
|
pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
|
|
|
|
|
|
|
|
/* PCI Express link has been reset */
|
|
|
|
pci_ers_result_t (*link_reset)(struct pci_dev *dev);
|
|
|
|
|
|
|
|
/* PCI slot has been reset */
|
|
|
|
pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
|
|
|
|
|
|
|
|
/* Device driver may resume normal operations */
|
|
|
|
void (*resume)(struct pci_dev *dev);
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ---------------------------------------------------------------- */
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
struct module;
|
|
|
|
struct pci_driver {
|
|
|
|
struct list_head node;
|
|
|
|
char *name;
|
|
|
|
const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
|
|
|
|
int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
|
|
|
|
void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
|
|
|
|
int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
|
2006-06-24 15:50:29 -06:00
|
|
|
int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
|
|
|
|
int (*resume_early) (struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
int (*resume) (struct pci_dev *dev); /* Device woken up */
|
2005-04-07 23:53:31 -06:00
|
|
|
void (*shutdown) (struct pci_dev *dev);
|
2005-11-16 16:10:41 -07:00
|
|
|
struct pci_error_handlers *err_handler;
|
2005-04-16 16:20:36 -06:00
|
|
|
struct device_driver driver;
|
|
|
|
struct pci_dynids dynids;
|
|
|
|
};
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-02-22 03:02:21 -07:00
|
|
|
/**
|
2008-03-10 12:43:34 -06:00
|
|
|
* DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
|
2008-02-22 03:02:21 -07:00
|
|
|
* @_table: device table name
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id array (a device table)
|
|
|
|
* in a generic manner.
|
|
|
|
*/
|
2008-03-10 12:43:34 -06:00
|
|
|
#define DEFINE_PCI_DEVICE_TABLE(_table) \
|
2008-02-22 03:02:21 -07:00
|
|
|
const struct pci_device_id _table[] __devinitconst
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* PCI_DEVICE - macro used to describe a specific pci device
|
|
|
|
* @vend: the 16 bit PCI Vendor ID
|
|
|
|
* @dev: the 16 bit PCI Device ID
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific device. The subvendor and subdevice fields will be set to
|
|
|
|
* PCI_ANY_ID.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE(vend,dev) \
|
|
|
|
.vendor = (vend), .device = (dev), \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
|
|
|
|
|
|
|
/**
|
|
|
|
* PCI_DEVICE_CLASS - macro used to describe a specific pci device class
|
|
|
|
* @dev_class: the class, subclass, prog-if triple for this device
|
|
|
|
* @dev_class_mask: the class mask for this device
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
2005-07-28 12:37:33 -06:00
|
|
|
* specific PCI class. The vendor, device, subvendor, and subdevice
|
2005-04-16 16:20:36 -06:00
|
|
|
* fields will be set to PCI_ANY_ID.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
|
|
|
|
.class = (dev_class), .class_mask = (dev_class_mask), \
|
|
|
|
.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
|
|
|
|
2006-12-04 16:14:45 -07:00
|
|
|
/**
|
|
|
|
* PCI_VDEVICE - macro used to describe a specific pci device in short form
|
2008-10-13 05:36:05 -06:00
|
|
|
* @vendor: the vendor name
|
|
|
|
* @device: the 16 bit PCI Device ID
|
2006-12-04 16:14:45 -07:00
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific PCI device. The subvendor, and subdevice fields will be set
|
|
|
|
* to PCI_ANY_ID. The macro allows the next field to follow as the device
|
|
|
|
* private data.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PCI_VDEVICE(vendor, device) \
|
|
|
|
PCI_VENDOR_ID_##vendor, (device), \
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* these external functions are only available when PCI support is enabled */
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
|
|
|
extern struct bus_type pci_bus_type;
|
|
|
|
|
|
|
|
/* Do NOT directly access these two variables, unless you are arch specific pci
|
|
|
|
* code, or pci core code. */
|
|
|
|
extern struct list_head pci_root_buses; /* list of all known PCI buses */
|
2007-07-16 00:39:39 -06:00
|
|
|
/* Some device drivers need know if pci is initiated */
|
|
|
|
extern int no_pci_devices(void);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
void pcibios_fixup_bus(struct pci_bus *);
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pcibios_enable_device(struct pci_dev *, int mask);
|
2008-01-30 16:21:33 -07:00
|
|
|
char *pcibios_setup(char *str);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Used only when drivers/pci/setup.c is used */
|
2006-06-12 18:06:02 -06:00
|
|
|
void pcibios_align_resource(void *, struct resource *, resource_size_t,
|
|
|
|
resource_size_t);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pcibios_update_irq(struct pci_dev *, int irq);
|
|
|
|
|
|
|
|
/* Generic PCI functions used internally */
|
|
|
|
|
|
|
|
extern struct pci_bus *pci_find_bus(int domain, int busnr);
|
2009-02-03 16:45:26 -07:00
|
|
|
void pci_bus_add_devices(const struct pci_bus *bus);
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
|
|
|
|
struct pci_ops *ops, void *sysdata);
|
2008-04-29 14:38:48 -06:00
|
|
|
static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
|
2008-01-30 16:21:33 -07:00
|
|
|
void *sysdata)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2005-04-28 01:25:45 -06:00
|
|
|
struct pci_bus *root_bus;
|
|
|
|
root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
|
|
|
|
if (root_bus)
|
|
|
|
pci_bus_add_devices(root_bus);
|
|
|
|
return root_bus;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_bus *pci_create_bus(struct device *parent, int bus,
|
|
|
|
struct pci_ops *ops, void *sysdata);
|
|
|
|
struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
|
|
|
|
int busnr);
|
2008-06-10 15:28:50 -06:00
|
|
|
struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
|
2008-10-20 17:40:52 -06:00
|
|
|
const char *name,
|
|
|
|
struct hotplug_slot *hotplug);
|
2008-06-10 15:28:50 -06:00
|
|
|
void pci_destroy_slot(struct pci_slot *slot);
|
2008-10-20 17:40:47 -06:00
|
|
|
void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
|
2005-04-16 16:20:36 -06:00
|
|
|
int pci_scan_slot(struct pci_bus *bus, int devfn);
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
|
2005-09-05 17:31:03 -06:00
|
|
|
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned int pci_scan_child_bus(struct pci_bus *bus);
|
2006-08-28 12:43:25 -06:00
|
|
|
int __must_check pci_bus_add_device(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_read_bridge_bases(struct pci_bus *child);
|
2008-01-30 16:21:33 -07:00
|
|
|
struct resource *pci_find_parent_resource(const struct pci_dev *dev,
|
|
|
|
struct resource *res);
|
2008-12-11 11:24:23 -07:00
|
|
|
u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
|
2005-04-16 16:20:36 -06:00
|
|
|
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
|
2008-12-16 21:36:55 -07:00
|
|
|
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
|
2005-04-16 16:20:36 -06:00
|
|
|
extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
|
|
|
|
extern void pci_dev_put(struct pci_dev *dev);
|
|
|
|
extern void pci_remove_bus(struct pci_bus *b);
|
|
|
|
extern void pci_remove_bus_device(struct pci_dev *dev);
|
2006-09-12 11:16:36 -06:00
|
|
|
extern void pci_stop_bus_device(struct pci_dev *dev);
|
2005-09-09 14:03:23 -06:00
|
|
|
void pci_setup_cardbus(struct pci_bus *bus);
|
PCI: optionally sort device lists breadth-first
Problem:
New Dell PowerEdge servers have 2 embedded ethernet ports, which are
labeled NIC1 and NIC2 on the chassis, in the BIOS setup screens, and
in the printed documentation. Assuming no other add-in ethernet ports
in the system, Linux 2.4 kernels name these eth0 and eth1
respectively. Many people have come to expect this naming. Linux 2.6
kernels name these eth1 and eth0 respectively (backwards from
expectations). I also have reports that various Sun and HP servers
have similar behavior.
Root cause:
Linux 2.4 kernels walk the pci_devices list, which happens to be
sorted in breadth-first order (or pcbios_find_device order on i386,
which most often is breadth-first also). 2.6 kernels have both the
pci_devices list and the pci_bus_type.klist_devices list, the latter
is what is walked at driver load time to match the pci_id tables; this
klist happens to be in depth-first order.
On systems where, for physical routing reasons, NIC1 appears on a
lower bus number than NIC2, but NIC2's bridge is discovered first in
the depth-first ordering, NIC2 will be discovered before NIC1. If the
list were sorted breadth-first, NIC1 would be discovered before NIC2.
A PowerEdge 1955 system has the following topology which easily
exhibits the difference between depth-first and breadth-first device
lists.
-[0000:00]-+-00.0 Intel Corporation 5000P Chipset Memory Controller Hub
+-02.0-[0000:03-08]--+-00.0-[0000:04-07]--+-00.0-[0000:05-06]----00.0-[0000:06]----00.0 Broadcom Corporation NetXtreme II BCM5708S Gigabit Ethernet (labeled NIC2, 2.4 kernel name eth1, 2.6 kernel name eth0)
+-1c.0-[0000:01-02]----00.0-[0000:02]----00.0 Broadcom Corporation NetXtreme II BCM5708S Gigabit Ethernet (labeled NIC1, 2.4 kernel name eth0, 2.6 kernel name eth1)
Other factors, such as device driver load order and the presence of
PCI slots at various points in the bus hierarchy further complicate
this problem; I'm not trying to solve those here, just restore the
device order, and thus basic behavior, that 2.4 kernels had.
Solution:
The solution can come in multiple steps.
Suggested fix #1: kernel
Patch below optionally sorts the two device lists into breadth-first
ordering to maintain compatibility with 2.4 kernels. It adds two new
command line options:
pci=bfsort
pci=nobfsort
to force the sort order, or not, as you wish. It also adds DMI checks
for the specific Dell systems which exhibit "backwards" ordering, to
make them "right".
Suggested fix #2: udev rules from userland
Many people also have the expectation that embedded NICs are always
discovered before add-in NICs (which this patch does not try to do).
Using the PCI IRQ Routing Table provided by system BIOS, it's easy to
determine which PCI devices are embedded, or if add-in, which PCI slot
they're in. I'm working on a tool that would allow udev to name
ethernet devices in ascending embedded, slot 1 .. slot N order,
subsort by PCI bus/dev/fn breadth-first. It'll be possible to use it
independent of udev as well for those distributions that don't use
udev in their installers.
Suggested fix #3: system board routing rules
One can constrain the system board layout to put NIC1 ahead of NIC2
regardless of breadth-first or depth-first discovery order. This adds
a significant level of complexity to board routing, and may not be
possible in all instances (witness the above systems from several
major manufacturers). I don't want to encourage this particular train
of thought too far, at the expense of not doing #1 or #2 above.
Feedback appreciated. Patch tested on a Dell PowerEdge 1955 blade
with 2.6.18.
You'll also note I took some liberty and temporarily break the klist
abstraction to simplify and speed up the sort algorithm. I think
that's both safe and appropriate in this instance.
Signed-off-by: Matt Domsch <Matt_Domsch@dell.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-09-29 14:23:23 -06:00
|
|
|
extern void pci_sort_breadthfirst(void);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Generic PCI functions exported to card drivers */
|
|
|
|
|
2007-10-29 07:48:09 -06:00
|
|
|
#ifdef CONFIG_PCI_LEGACY
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
|
|
|
|
unsigned int device,
|
2008-08-26 09:20:34 -06:00
|
|
|
struct pci_dev *from);
|
2007-10-29 07:48:09 -06:00
|
|
|
#endif /* CONFIG_PCI_LEGACY */
|
|
|
|
|
2008-08-03 12:02:12 -06:00
|
|
|
enum pci_lost_interrupt_reason {
|
|
|
|
PCI_LOST_IRQ_NO_INFORMATION = 0,
|
|
|
|
PCI_LOST_IRQ_DISABLE_MSI,
|
|
|
|
PCI_LOST_IRQ_DISABLE_MSIX,
|
|
|
|
PCI_LOST_IRQ_DISABLE_ACPI,
|
|
|
|
};
|
|
|
|
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
|
2008-01-30 16:21:33 -07:00
|
|
|
int pci_find_capability(struct pci_dev *dev, int cap);
|
|
|
|
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
|
|
|
|
int pci_find_ext_capability(struct pci_dev *dev, int cap);
|
|
|
|
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
|
|
|
|
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
|
2006-10-16 17:20:21 -06:00
|
|
|
struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-10-21 11:24:12 -06:00
|
|
|
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
|
|
|
|
struct pci_dev *from);
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned int ss_vendor, unsigned int ss_device,
|
2008-08-26 09:20:34 -06:00
|
|
|
struct pci_dev *from);
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
|
2009-10-12 13:14:00 -06:00
|
|
|
struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
|
|
|
|
unsigned int devfn);
|
|
|
|
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
|
|
|
|
unsigned int devfn)
|
|
|
|
{
|
|
|
|
return pci_get_domain_bus_and_slot(0, bus, devfn);
|
|
|
|
}
|
2008-01-30 16:21:33 -07:00
|
|
|
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
|
2005-04-16 16:20:36 -06:00
|
|
|
int pci_dev_present(const struct pci_device_id *ids);
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u8 *val);
|
|
|
|
int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u16 *val);
|
|
|
|
int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u32 *val);
|
|
|
|
int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u8 val);
|
|
|
|
int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u16 val);
|
|
|
|
int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u32 val);
|
2009-04-23 20:45:17 -06:00
|
|
|
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
|
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
|
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_read_config_dword(struct pci_dev *dev, int where,
|
|
|
|
u32 *val)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
|
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
|
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_write_config_dword(struct pci_dev *dev, int where,
|
|
|
|
u32 val)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2008-01-30 16:21:33 -07:00
|
|
|
return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_enable_device(struct pci_dev *dev);
|
2007-12-19 21:28:08 -07:00
|
|
|
int __must_check pci_enable_device_io(struct pci_dev *dev);
|
|
|
|
int __must_check pci_enable_device_mem(struct pci_dev *dev);
|
2007-07-26 23:43:35 -06:00
|
|
|
int __must_check pci_reenable_device(struct pci_dev *);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
int __must_check pcim_enable_device(struct pci_dev *pdev);
|
|
|
|
void pcim_pin_device(struct pci_dev *pdev);
|
|
|
|
|
2009-04-03 01:41:46 -06:00
|
|
|
static inline int pci_is_enabled(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return (atomic_read(&pdev->enable_cnt) > 0);
|
|
|
|
}
|
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
static inline int pci_is_managed(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pdev->is_managed;
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_disable_device(struct pci_dev *dev);
|
|
|
|
void pci_set_master(struct pci_dev *dev);
|
2008-12-22 20:08:29 -07:00
|
|
|
void pci_clear_master(struct pci_dev *dev);
|
2007-04-06 15:39:36 -06:00
|
|
|
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
|
2009-09-22 02:34:48 -06:00
|
|
|
int pci_set_cacheline_size(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
#define HAVE_PCI_SET_MWI
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_set_mwi(struct pci_dev *dev);
|
2007-07-09 12:55:54 -06:00
|
|
|
int pci_try_set_mwi(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_clear_mwi(struct pci_dev *dev);
|
2005-08-15 13:23:41 -06:00
|
|
|
void pci_intx(struct pci_dev *dev, int enable);
|
2007-03-05 01:30:07 -07:00
|
|
|
void pci_msi_off(struct pci_dev *dev);
|
2005-09-09 16:43:46 -06:00
|
|
|
int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
|
|
|
|
int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
|
2008-02-04 23:27:55 -07:00
|
|
|
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
|
2008-02-04 23:28:14 -07:00
|
|
|
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
|
2007-05-15 05:59:13 -06:00
|
|
|
int pcix_get_max_mmrbc(struct pci_dev *dev);
|
|
|
|
int pcix_get_mmrbc(struct pci_dev *dev);
|
|
|
|
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
|
2007-08-14 04:43:48 -06:00
|
|
|
int pcie_get_readrq(struct pci_dev *dev);
|
2007-05-15 05:59:13 -06:00
|
|
|
int pcie_set_readrq(struct pci_dev *dev, int rq);
|
2009-06-13 01:52:13 -06:00
|
|
|
int __pci_reset_function(struct pci_dev *dev);
|
2008-10-21 03:38:25 -06:00
|
|
|
int pci_reset_function(struct pci_dev *dev);
|
2008-11-21 11:38:52 -07:00
|
|
|
void pci_update_resource(struct pci_dev *dev, int resno);
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
|
2006-12-17 18:31:06 -07:00
|
|
|
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* ROM control related routines */
|
2008-09-23 10:25:10 -06:00
|
|
|
int pci_enable_rom(struct pci_dev *pdev);
|
|
|
|
void pci_disable_rom(struct pci_dev *pdev);
|
2005-08-08 22:20:10 -06:00
|
|
|
void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
|
2009-01-29 12:12:47 -07:00
|
|
|
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Power management related routines */
|
|
|
|
int pci_save_state(struct pci_dev *dev);
|
|
|
|
int pci_restore_state(struct pci_dev *dev);
|
2009-03-26 15:51:40 -06:00
|
|
|
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
|
2005-09-09 16:43:46 -06:00
|
|
|
int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
|
|
|
|
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
|
2008-07-19 06:39:24 -06:00
|
|
|
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
|
2008-08-07 16:14:24 -06:00
|
|
|
void pci_pme_active(struct pci_dev *dev, bool enable);
|
2009-06-16 16:16:15 -06:00
|
|
|
int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
|
2008-08-18 13:38:00 -06:00
|
|
|
int pci_wake_from_d3(struct pci_dev *dev, bool enable);
|
2008-07-19 06:39:24 -06:00
|
|
|
pci_power_t pci_target_state(struct pci_dev *dev);
|
2008-07-06 19:35:26 -06:00
|
|
|
int pci_prepare_to_sleep(struct pci_dev *dev);
|
|
|
|
int pci_back_from_sleep(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-07-16 22:27:10 -06:00
|
|
|
/* Functions for PCI Hotplug drivers to use */
|
2008-01-30 16:21:33 -07:00
|
|
|
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
|
2009-03-20 14:56:25 -06:00
|
|
|
#ifdef CONFIG_HOTPLUG
|
|
|
|
unsigned int pci_rescan_bus(struct pci_bus *bus);
|
|
|
|
#endif
|
2007-07-16 22:27:10 -06:00
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
/* Vital product data routines */
|
|
|
|
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
|
|
|
|
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
|
2008-12-18 10:17:16 -07:00
|
|
|
int pci_vpd_truncate(struct pci_dev *dev, size_t size);
|
2008-12-18 10:17:16 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
|
2009-02-18 11:44:29 -07:00
|
|
|
void pci_bus_assign_resources(const struct pci_bus *bus);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_bus_size_bridges(struct pci_bus *bus);
|
|
|
|
int pci_claim_resource(struct pci_dev *, int);
|
|
|
|
void pci_assign_unassigned_resources(void);
|
|
|
|
void pdev_enable_device(struct pci_dev *);
|
|
|
|
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
|
2008-03-04 11:56:47 -07:00
|
|
|
int pci_enable_resources(struct pci_dev *, int mask);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
|
|
|
|
int (*)(struct pci_dev *, u8, u8));
|
|
|
|
#define HAVE_PCI_REQ_REGIONS 2
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_request_regions(struct pci_dev *, const char *);
|
2008-10-22 20:55:31 -06:00
|
|
|
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_release_regions(struct pci_dev *);
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_request_region(struct pci_dev *, int, const char *);
|
2008-10-22 20:55:31 -06:00
|
|
|
int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_release_region(struct pci_dev *, int);
|
2006-12-17 18:31:06 -07:00
|
|
|
int pci_request_selected_regions(struct pci_dev *, int, const char *);
|
2008-10-22 20:55:31 -06:00
|
|
|
int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
|
2006-12-17 18:31:06 -07:00
|
|
|
void pci_release_selected_regions(struct pci_dev *, int);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* drivers/pci/bus.c */
|
2006-08-14 23:43:17 -06:00
|
|
|
int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
|
|
|
|
struct resource *res, resource_size_t size,
|
|
|
|
resource_size_t align, resource_size_t min,
|
|
|
|
unsigned int type_mask,
|
|
|
|
void (*alignf)(void *, struct resource *,
|
|
|
|
resource_size_t, resource_size_t),
|
|
|
|
void *alignf_data);
|
2005-04-16 16:20:36 -06:00
|
|
|
void pci_enable_bridges(struct pci_bus *bus);
|
|
|
|
|
2005-10-27 15:12:54 -06:00
|
|
|
/* Proper probing supporting hot-pluggable devices */
|
2007-01-15 12:50:02 -07:00
|
|
|
int __must_check __pci_register_driver(struct pci_driver *, struct module *,
|
|
|
|
const char *mod_name);
|
2008-07-30 13:07:04 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
|
|
|
|
*/
|
|
|
|
#define pci_register_driver(driver) \
|
|
|
|
__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
|
2005-10-27 15:12:54 -06:00
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
void pci_unregister_driver(struct pci_driver *dev);
|
|
|
|
void pci_remove_behind_bridge(struct pci_dev *dev);
|
|
|
|
struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
|
2009-09-03 00:26:36 -06:00
|
|
|
int pci_add_dynid(struct pci_driver *drv,
|
|
|
|
unsigned int vendor, unsigned int device,
|
|
|
|
unsigned int subvendor, unsigned int subdevice,
|
|
|
|
unsigned int class, unsigned int class_mask,
|
|
|
|
unsigned long driver_data);
|
2008-01-30 16:21:33 -07:00
|
|
|
const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
|
|
|
|
struct pci_dev *dev);
|
|
|
|
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
|
|
|
|
int pass);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-06-15 23:34:38 -06:00
|
|
|
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
|
2005-08-17 22:33:01 -06:00
|
|
|
void *userdata);
|
2008-04-28 17:27:23 -06:00
|
|
|
int pci_cfg_space_size_ext(struct pci_dev *dev);
|
2005-12-13 00:09:16 -07:00
|
|
|
int pci_cfg_space_size(struct pci_dev *dev);
|
2008-01-30 16:21:33 -07:00
|
|
|
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
|
2005-08-17 22:33:01 -06:00
|
|
|
|
2009-08-10 23:52:06 -06:00
|
|
|
int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
|
|
|
unsigned int command_bits, bool change_bridge);
|
2005-04-16 16:20:36 -06:00
|
|
|
/* kmem_cache style wrapper around pci_alloc_consistent() */
|
|
|
|
|
|
|
|
#include <linux/dmapool.h>
|
|
|
|
|
|
|
|
#define pci_pool dma_pool
|
|
|
|
#define pci_pool_create(name, pdev, size, align, allocation) \
|
|
|
|
dma_pool_create(name, &pdev->dev, size, align, allocation)
|
|
|
|
#define pci_pool_destroy(pool) dma_pool_destroy(pool)
|
|
|
|
#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
|
|
|
|
#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
|
|
|
|
|
2005-06-02 13:55:50 -06:00
|
|
|
enum pci_dma_burst_strategy {
|
|
|
|
PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
|
|
|
|
strategy_parameter is N/A */
|
|
|
|
PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
|
|
|
|
byte boundaries */
|
|
|
|
PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
|
|
|
|
strategy_parameter byte boundaries */
|
|
|
|
};
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
struct msix_entry {
|
2008-08-15 20:36:45 -06:00
|
|
|
u32 vector; /* kernel uses to write allocated vector */
|
2005-04-16 16:20:36 -06:00
|
|
|
u16 entry; /* driver uses to specify entry, OS writes */
|
|
|
|
};
|
|
|
|
|
2006-10-04 03:16:33 -06:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifndef CONFIG_PCI_MSI
|
2009-03-17 06:54:10 -06:00
|
|
|
static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
|
2008-01-30 16:21:33 -07:00
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2008-04-23 15:58:09 -06:00
|
|
|
static inline void pci_msi_shutdown(struct pci_dev *dev)
|
|
|
|
{ }
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void pci_disable_msi(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
2009-01-23 16:21:14 -07:00
|
|
|
static inline int pci_msix_table_size(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_enable_msix(struct pci_dev *dev,
|
|
|
|
struct msix_entry *entries, int nvec)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2008-04-23 15:58:09 -06:00
|
|
|
static inline void pci_msix_shutdown(struct pci_dev *dev)
|
|
|
|
{ }
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void pci_disable_msix(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline void pci_restore_msi_state(struct pci_dev *dev)
|
|
|
|
{ }
|
2008-11-10 15:31:05 -07:00
|
|
|
static inline int pci_msi_enabled(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
#else
|
2009-03-17 06:54:10 -06:00
|
|
|
extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
|
2008-04-23 15:58:09 -06:00
|
|
|
extern void pci_msi_shutdown(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
extern void pci_disable_msi(struct pci_dev *dev);
|
2009-01-23 16:21:14 -07:00
|
|
|
extern int pci_msix_table_size(struct pci_dev *dev);
|
2008-01-30 16:21:33 -07:00
|
|
|
extern int pci_enable_msix(struct pci_dev *dev,
|
2005-04-16 16:20:36 -06:00
|
|
|
struct msix_entry *entries, int nvec);
|
2008-04-23 15:58:09 -06:00
|
|
|
extern void pci_msix_shutdown(struct pci_dev *dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
extern void pci_disable_msix(struct pci_dev *dev);
|
|
|
|
extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
|
2007-11-07 14:43:59 -07:00
|
|
|
extern void pci_restore_msi_state(struct pci_dev *dev);
|
2008-11-10 15:31:05 -07:00
|
|
|
extern int pci_msi_enabled(void);
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif
|
|
|
|
|
2008-11-10 15:30:55 -07:00
|
|
|
#ifndef CONFIG_PCIEASPM
|
|
|
|
static inline int pcie_aspm_enabled(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
extern int pcie_aspm_enabled(void);
|
|
|
|
#endif
|
|
|
|
|
2009-04-22 16:52:09 -06:00
|
|
|
#ifndef CONFIG_PCIE_ECRC
|
|
|
|
static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
static inline void pcie_ecrc_get_policy(char *str) {};
|
|
|
|
#else
|
|
|
|
extern void pcie_set_ecrc_checking(struct pci_dev *dev);
|
|
|
|
extern void pcie_ecrc_get_policy(char *str);
|
|
|
|
#endif
|
|
|
|
|
2009-03-17 06:54:10 -06:00
|
|
|
#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
|
|
|
|
|
2006-10-04 03:16:55 -06:00
|
|
|
#ifdef CONFIG_HT_IRQ
|
|
|
|
/* The functions a driver should call */
|
|
|
|
int ht_create_irq(struct pci_dev *dev, int idx);
|
|
|
|
void ht_destroy_irq(unsigned int irq);
|
|
|
|
#endif /* CONFIG_HT_IRQ */
|
|
|
|
|
2005-09-27 02:21:55 -06:00
|
|
|
extern void pci_block_user_cfg_access(struct pci_dev *dev);
|
|
|
|
extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
|
|
|
|
|
2005-07-28 12:37:33 -06:00
|
|
|
/*
|
|
|
|
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
|
|
|
|
* a PCI domain is defined to be a set of PCI busses which share
|
|
|
|
* configuration space.
|
|
|
|
*/
|
2007-10-11 14:57:27 -06:00
|
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
|
|
extern int pci_domains_supported;
|
|
|
|
#else
|
|
|
|
enum { pci_domains_supported = 0 };
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_domain_nr(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-07-28 12:37:33 -06:00
|
|
|
static inline int pci_proc_domain(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2007-10-11 14:57:27 -06:00
|
|
|
#endif /* CONFIG_PCI_DOMAINS */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-07-28 12:37:33 -06:00
|
|
|
#else /* CONFIG_PCI is not enabled */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If the system does not have PCI, clearly these return errors. Define
|
|
|
|
* these as simple inline functions to avoid hair in drivers.
|
|
|
|
*/
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
#define _PCI_NOP(o, s, t) \
|
|
|
|
static inline int pci_##o##_config_##s(struct pci_dev *dev, \
|
|
|
|
int where, t val) \
|
2005-04-16 16:20:36 -06:00
|
|
|
{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
|
2008-01-30 16:21:33 -07:00
|
|
|
|
|
|
|
#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
|
|
|
|
_PCI_NOP(o, word, u16 x) \
|
|
|
|
_PCI_NOP(o, dword, u32 x)
|
2005-04-16 16:20:36 -06:00
|
|
|
_PCI_NOP_ALL(read, *)
|
|
|
|
_PCI_NOP_ALL(write,)
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline struct pci_dev *pci_find_device(unsigned int vendor,
|
|
|
|
unsigned int device,
|
2008-08-26 09:20:34 -06:00
|
|
|
struct pci_dev *from)
|
2008-01-30 16:21:33 -07:00
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-10-21 11:24:12 -06:00
|
|
|
static inline struct pci_dev *pci_get_device(unsigned int vendor,
|
2008-01-30 16:21:33 -07:00
|
|
|
unsigned int device,
|
|
|
|
struct pci_dev *from)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2006-10-21 11:24:12 -06:00
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
|
|
|
|
unsigned int device,
|
|
|
|
unsigned int ss_vendor,
|
|
|
|
unsigned int ss_device,
|
2008-08-26 09:20:34 -06:00
|
|
|
struct pci_dev *from)
|
2008-01-30 16:21:33 -07:00
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline struct pci_dev *pci_get_class(unsigned int class,
|
|
|
|
struct pci_dev *from)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
#define pci_dev_present(ids) (0)
|
2007-07-16 00:39:39 -06:00
|
|
|
#define no_pci_devices() (1)
|
2005-04-16 16:20:36 -06:00
|
|
|
#define pci_dev_put(dev) do { } while (0)
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void pci_set_master(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline int pci_enable_device(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pci_disable_device(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2008-06-30 12:35:53 -06:00
|
|
|
static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2008-02-04 23:27:55 -07:00
|
|
|
static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
|
|
|
|
unsigned int size)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2008-02-04 23:28:14 -07:00
|
|
|
static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
|
|
|
|
unsigned long mask)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_assign_resource(struct pci_dev *dev, int i)
|
|
|
|
{
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int __pci_register_driver(struct pci_driver *drv,
|
|
|
|
struct module *owner)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_register_driver(struct pci_driver *drv)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pci_unregister_driver(struct pci_driver *drv)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline int pci_find_capability(struct pci_dev *dev, int cap)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
|
|
|
|
int cap)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Power management related routines */
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_save_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_restore_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline pci_power_t pci_choose_state(struct pci_dev *dev,
|
|
|
|
pm_message_t state)
|
|
|
|
{
|
|
|
|
return PCI_D0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
|
|
|
|
int enable)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
|
|
|
|
{
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pci_release_regions(struct pci_dev *dev)
|
|
|
|
{ }
|
2007-04-01 11:13:58 -06:00
|
|
|
|
2005-07-29 13:16:27 -06:00
|
|
|
#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void pci_block_user_cfg_access(struct pci_dev *dev)
|
|
|
|
{ }
|
|
|
|
|
|
|
|
static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
|
|
|
|
{ }
|
2005-09-27 02:21:55 -06:00
|
|
|
|
2007-07-01 13:06:37 -06:00
|
|
|
static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
|
|
|
|
{ return NULL; }
|
|
|
|
|
|
|
|
static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
|
|
|
|
unsigned int devfn)
|
|
|
|
{ return NULL; }
|
|
|
|
|
|
|
|
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
|
|
|
|
unsigned int devfn)
|
|
|
|
{ return NULL; }
|
|
|
|
|
2005-07-28 12:37:33 -06:00
|
|
|
#endif /* CONFIG_PCI */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-07-28 12:37:33 -06:00
|
|
|
/* Include architecture-dependent settings and functions */
|
|
|
|
|
|
|
|
#include <asm/pci.h>
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-04-23 21:48:32 -06:00
|
|
|
#ifndef PCIBIOS_MAX_MEM_32
|
|
|
|
#define PCIBIOS_MAX_MEM_32 (-1)
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* these helpers provide future and backwards compatibility
|
|
|
|
* for accessing popular PCI BAR info */
|
2008-01-30 16:21:33 -07:00
|
|
|
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
|
|
|
|
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
|
|
|
|
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
|
2005-04-16 16:20:36 -06:00
|
|
|
#define pci_resource_len(dev,bar) \
|
2008-01-30 16:21:33 -07:00
|
|
|
((pci_resource_start((dev), (bar)) == 0 && \
|
|
|
|
pci_resource_end((dev), (bar)) == \
|
|
|
|
pci_resource_start((dev), (bar))) ? 0 : \
|
|
|
|
\
|
|
|
|
(pci_resource_end((dev), (bar)) - \
|
|
|
|
pci_resource_start((dev), (bar)) + 1))
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Similar to the helpers above, these manipulate per-pci_dev
|
|
|
|
* driver-specific data. They are really just a wrapper around
|
|
|
|
* the generic device structure functions of these calls.
|
|
|
|
*/
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void *pci_get_drvdata(struct pci_dev *pdev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
return dev_get_drvdata(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2008-01-30 16:21:33 -07:00
|
|
|
static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
dev_set_drvdata(&pdev->dev, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If you want to know what to call your pci_dev, ask this function.
|
|
|
|
* Again, it's a wrapper around the generic device.
|
|
|
|
*/
|
2009-06-24 06:22:30 -06:00
|
|
|
static inline const char *pci_name(const struct pci_dev *pdev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2008-07-03 10:49:39 -06:00
|
|
|
return dev_name(&pdev->dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2005-05-13 01:44:10 -06:00
|
|
|
|
|
|
|
/* Some archs don't want to expose struct resource to userland as-is
|
|
|
|
* in sysfs and /proc
|
|
|
|
*/
|
|
|
|
#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
|
|
|
|
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
2008-01-30 16:21:33 -07:00
|
|
|
const struct resource *rsrc, resource_size_t *start,
|
2006-06-12 18:06:02 -06:00
|
|
|
resource_size_t *end)
|
2005-05-13 01:44:10 -06:00
|
|
|
{
|
|
|
|
*start = rsrc->start;
|
|
|
|
*end = rsrc->end;
|
|
|
|
}
|
|
|
|
#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
|
|
|
|
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
* The world is not perfect and supplies us with broken PCI devices.
|
|
|
|
* For at least a part of these bugs we need a work-around, so both
|
|
|
|
* generic (drivers/pci/quirks.c) and per-architecture code can define
|
|
|
|
* fixup hooks to be called for particular buggy devices.
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct pci_fixup {
|
|
|
|
u16 vendor, device; /* You can use PCI_ANY_ID here of course */
|
|
|
|
void (*hook)(struct pci_dev *dev);
|
|
|
|
};
|
|
|
|
|
|
|
|
enum pci_fixup_pass {
|
|
|
|
pci_fixup_early, /* Before probing BARs */
|
|
|
|
pci_fixup_header, /* After reading configuration header */
|
|
|
|
pci_fixup_final, /* Final phase of device fixups */
|
|
|
|
pci_fixup_enable, /* pci_enable_device() time */
|
2008-05-15 13:51:31 -06:00
|
|
|
pci_fixup_resume, /* pci_device_resume() */
|
|
|
|
pci_fixup_suspend, /* pci_device_suspend */
|
|
|
|
pci_fixup_resume_early, /* pci_device_resume_early() */
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Anonymous variables would be nice... */
|
|
|
|
#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
|
2008-01-24 14:16:20 -07:00
|
|
|
static const struct pci_fixup __pci_fixup_##name __used \
|
2005-04-16 16:20:36 -06:00
|
|
|
__attribute__((__section__(#section))) = { vendor, device, hook };
|
|
|
|
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
|
|
|
|
vendor##device##hook, vendor, device, hook)
|
|
|
|
#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
|
|
|
|
vendor##device##hook, vendor, device, hook)
|
|
|
|
#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
|
|
|
|
vendor##device##hook, vendor, device, hook)
|
|
|
|
#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
|
|
|
|
vendor##device##hook, vendor, device, hook)
|
2006-12-04 16:14:45 -07:00
|
|
|
#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
|
|
|
|
resume##vendor##device##hook, vendor, device, hook)
|
2008-05-15 13:51:31 -06:00
|
|
|
#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
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resume_early##vendor##device##hook, vendor, device, hook)
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#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
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DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
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suspend##vendor##device##hook, vendor, device, hook)
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2005-04-16 16:20:36 -06:00
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void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
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2008-01-30 16:21:33 -07:00
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void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
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2007-02-11 08:41:31 -07:00
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void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
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2008-01-30 16:21:33 -07:00
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void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
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2007-02-11 08:41:31 -07:00
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int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
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2008-03-12 00:26:34 -06:00
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int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
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const char *name);
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2007-03-09 03:45:58 -07:00
|
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void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
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2007-02-11 08:41:31 -07:00
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2005-04-16 16:20:36 -06:00
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extern int pci_pci_problems;
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2006-10-01 00:27:03 -06:00
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#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
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2005-04-16 16:20:36 -06:00
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#define PCIPCI_TRITON 2
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#define PCIPCI_NATOMA 4
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#define PCIPCI_VIAETBF 8
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#define PCIPCI_VSFX 16
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2006-10-01 00:27:03 -06:00
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#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
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#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
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2005-04-16 16:20:36 -06:00
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2007-02-05 17:36:06 -07:00
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extern unsigned long pci_cardbus_io_size;
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extern unsigned long pci_cardbus_mem_size;
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2009-12-14 07:13:44 -07:00
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extern u8 __devinitdata pci_dfl_cache_line_size;
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2009-10-26 14:20:44 -06:00
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extern u8 pci_cache_line_size;
|
2007-02-05 17:36:06 -07:00
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2009-09-09 15:09:24 -06:00
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extern unsigned long pci_hotplug_io_size;
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extern unsigned long pci_hotplug_mem_size;
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|
2008-05-05 12:25:47 -06:00
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int pcibios_add_platform_entries(struct pci_dev *dev);
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|
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void pcibios_disable_device(struct pci_dev *dev);
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|
|
int pcibios_set_pcie_reset_state(struct pci_dev *dev,
|
|
|
|
enum pcie_reset_state state);
|
2007-05-07 20:03:07 -06:00
|
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|
2008-02-15 02:27:20 -07:00
|
|
|
#ifdef CONFIG_PCI_MMCONFIG
|
2008-02-29 00:56:50 -07:00
|
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|
extern void __init pci_mmcfg_early_init(void);
|
2008-02-15 02:27:20 -07:00
|
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|
extern void __init pci_mmcfg_late_init(void);
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|
|
#else
|
2008-02-29 00:56:50 -07:00
|
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|
static inline void pci_mmcfg_early_init(void) { }
|
2008-02-15 02:27:20 -07:00
|
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|
static inline void pci_mmcfg_late_init(void) { }
|
|
|
|
#endif
|
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|
2008-11-10 15:30:50 -07:00
|
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|
int pci_ext_cfg_avail(struct pci_dev *dev);
|
|
|
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|
2008-12-01 15:30:30 -07:00
|
|
|
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
|
2008-09-28 17:36:11 -06:00
|
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|
2009-03-19 21:25:15 -06:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
|
|
|
|
extern void pci_disable_sriov(struct pci_dev *dev);
|
2009-03-19 21:25:16 -06:00
|
|
|
extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
|
2009-03-19 21:25:15 -06:00
|
|
|
#else
|
|
|
|
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
|
|
|
|
{
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
static inline void pci_disable_sriov(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
}
|
2009-03-19 21:25:16 -06:00
|
|
|
static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
2009-03-19 21:25:15 -06:00
|
|
|
#endif
|
|
|
|
|
2009-06-15 20:01:25 -06:00
|
|
|
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
|
|
|
|
extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
|
|
|
|
extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
|
|
|
|
#endif
|
|
|
|
|
2009-11-10 22:29:54 -07:00
|
|
|
/**
|
|
|
|
* pci_pcie_cap - get the saved PCIe capability offset
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* PCIe capability offset is calculated at PCI device initialization
|
|
|
|
* time and saved in the data structure. This function returns saved
|
|
|
|
* PCIe capability offset. Using this instead of pci_find_capability()
|
|
|
|
* reduces unnecessary search in the PCI configuration space. If you
|
|
|
|
* need to calculate PCIe capability offset from raw device for some
|
|
|
|
* reasons, please use pci_find_capability() instead.
|
|
|
|
*/
|
|
|
|
static inline int pci_pcie_cap(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return dev->pcie_cap;
|
|
|
|
}
|
|
|
|
|
2009-11-10 22:35:22 -07:00
|
|
|
/**
|
|
|
|
* pci_is_pcie - check if the PCI device is PCI Express capable
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Retrun true if the PCI device is PCI Express capable, false otherwise.
|
|
|
|
*/
|
|
|
|
static inline bool pci_is_pcie(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return !!pci_pcie_cap(dev);
|
|
|
|
}
|
|
|
|
|
2009-12-04 13:15:21 -07:00
|
|
|
void pci_request_acs(void);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* LINUX_PCI_H */
|