2020-05-13 08:07:22 -06:00
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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// Copyright (C) 2016-2018, Allwinner Technology CO., LTD.
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// Copyright (C) 2019-2020, Cerno
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#include <linux/bitfield.h>
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-iommu.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define IOMMU_RESET_REG 0x010
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#define IOMMU_ENABLE_REG 0x020
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#define IOMMU_ENABLE_ENABLE BIT(0)
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#define IOMMU_BYPASS_REG 0x030
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#define IOMMU_AUTO_GATING_REG 0x040
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#define IOMMU_AUTO_GATING_ENABLE BIT(0)
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#define IOMMU_WBUF_CTRL_REG 0x044
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#define IOMMU_OOO_CTRL_REG 0x048
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#define IOMMU_4KB_BDY_PRT_CTRL_REG 0x04c
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#define IOMMU_TTB_REG 0x050
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#define IOMMU_TLB_ENABLE_REG 0x060
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#define IOMMU_TLB_PREFETCH_REG 0x070
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#define IOMMU_TLB_PREFETCH_MASTER_ENABLE(m) BIT(m)
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#define IOMMU_TLB_FLUSH_REG 0x080
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#define IOMMU_TLB_FLUSH_PTW_CACHE BIT(17)
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#define IOMMU_TLB_FLUSH_MACRO_TLB BIT(16)
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#define IOMMU_TLB_FLUSH_MICRO_TLB(i) (BIT(i) & GENMASK(5, 0))
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#define IOMMU_TLB_IVLD_ADDR_REG 0x090
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#define IOMMU_TLB_IVLD_ADDR_MASK_REG 0x094
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#define IOMMU_TLB_IVLD_ENABLE_REG 0x098
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#define IOMMU_TLB_IVLD_ENABLE_ENABLE BIT(0)
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#define IOMMU_PC_IVLD_ADDR_REG 0x0a0
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#define IOMMU_PC_IVLD_ENABLE_REG 0x0a8
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#define IOMMU_PC_IVLD_ENABLE_ENABLE BIT(0)
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#define IOMMU_DM_AUT_CTRL_REG(d) (0x0b0 + ((d) / 2) * 4)
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#define IOMMU_DM_AUT_CTRL_RD_UNAVAIL(d, m) (1 << (((d & 1) * 16) + ((m) * 2)))
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#define IOMMU_DM_AUT_CTRL_WR_UNAVAIL(d, m) (1 << (((d & 1) * 16) + ((m) * 2) + 1))
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#define IOMMU_DM_AUT_OVWT_REG 0x0d0
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#define IOMMU_INT_ENABLE_REG 0x100
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#define IOMMU_INT_CLR_REG 0x104
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#define IOMMU_INT_STA_REG 0x108
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#define IOMMU_INT_ERR_ADDR_REG(i) (0x110 + (i) * 4)
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#define IOMMU_INT_ERR_ADDR_L1_REG 0x130
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#define IOMMU_INT_ERR_ADDR_L2_REG 0x134
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#define IOMMU_INT_ERR_DATA_REG(i) (0x150 + (i) * 4)
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#define IOMMU_L1PG_INT_REG 0x0180
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#define IOMMU_L2PG_INT_REG 0x0184
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#define IOMMU_INT_INVALID_L2PG BIT(17)
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#define IOMMU_INT_INVALID_L1PG BIT(16)
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#define IOMMU_INT_MASTER_PERMISSION(m) BIT(m)
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#define IOMMU_INT_MASTER_MASK (IOMMU_INT_MASTER_PERMISSION(0) | \
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IOMMU_INT_MASTER_PERMISSION(1) | \
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IOMMU_INT_MASTER_PERMISSION(2) | \
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IOMMU_INT_MASTER_PERMISSION(3) | \
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IOMMU_INT_MASTER_PERMISSION(4) | \
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IOMMU_INT_MASTER_PERMISSION(5))
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#define IOMMU_INT_MASK (IOMMU_INT_INVALID_L1PG | \
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IOMMU_INT_INVALID_L2PG | \
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IOMMU_INT_MASTER_MASK)
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#define PT_ENTRY_SIZE sizeof(u32)
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#define NUM_DT_ENTRIES 4096
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#define DT_SIZE (NUM_DT_ENTRIES * PT_ENTRY_SIZE)
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#define NUM_PT_ENTRIES 256
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#define PT_SIZE (NUM_PT_ENTRIES * PT_ENTRY_SIZE)
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struct sun50i_iommu {
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struct iommu_device iommu;
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/* Lock to modify the IOMMU registers */
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spinlock_t iommu_lock;
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struct device *dev;
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void __iomem *base;
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struct reset_control *reset;
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struct clk *clk;
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struct iommu_domain *domain;
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struct iommu_group *group;
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struct kmem_cache *pt_pool;
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};
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struct sun50i_iommu_domain {
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struct iommu_domain domain;
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/* Number of devices attached to the domain */
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refcount_t refcnt;
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/* L1 Page Table */
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u32 *dt;
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dma_addr_t dt_dma;
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struct sun50i_iommu *iommu;
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};
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static struct sun50i_iommu_domain *to_sun50i_domain(struct iommu_domain *domain)
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{
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return container_of(domain, struct sun50i_iommu_domain, domain);
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}
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static struct sun50i_iommu *sun50i_iommu_from_dev(struct device *dev)
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{
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return dev_iommu_priv_get(dev);
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}
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static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset)
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{
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return readl(iommu->base + offset);
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}
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static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value)
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{
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writel(value, iommu->base + offset);
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}
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/*
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* The Allwinner H6 IOMMU uses a 2-level page table.
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*
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* The first level is the usual Directory Table (DT), that consists of
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* 4096 4-bytes Directory Table Entries (DTE), each pointing to a Page
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* Table (PT).
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*
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* Each PT consits of 256 4-bytes Page Table Entries (PTE), each
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* pointing to a 4kB page of physical memory.
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*
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* The IOMMU supports a single DT, pointed by the IOMMU_TTB_REG
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* register that contains its physical address.
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*/
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#define SUN50I_IOVA_DTE_MASK GENMASK(31, 20)
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#define SUN50I_IOVA_PTE_MASK GENMASK(19, 12)
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#define SUN50I_IOVA_PAGE_MASK GENMASK(11, 0)
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static u32 sun50i_iova_get_dte_index(dma_addr_t iova)
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{
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return FIELD_GET(SUN50I_IOVA_DTE_MASK, iova);
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}
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static u32 sun50i_iova_get_pte_index(dma_addr_t iova)
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{
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return FIELD_GET(SUN50I_IOVA_PTE_MASK, iova);
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}
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static u32 sun50i_iova_get_page_offset(dma_addr_t iova)
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{
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return FIELD_GET(SUN50I_IOVA_PAGE_MASK, iova);
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}
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/*
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* Each Directory Table Entry has a Page Table address and a valid
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* bit:
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* +---------------------+-----------+-+
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* | PT address | Reserved |V|
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* +---------------------+-----------+-+
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* 31:10 - Page Table address
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* 9:2 - Reserved
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* 1:0 - 1 if the entry is valid
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*/
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#define SUN50I_DTE_PT_ADDRESS_MASK GENMASK(31, 10)
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#define SUN50I_DTE_PT_ATTRS GENMASK(1, 0)
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#define SUN50I_DTE_PT_VALID 1
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static phys_addr_t sun50i_dte_get_pt_address(u32 dte)
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{
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return (phys_addr_t)dte & SUN50I_DTE_PT_ADDRESS_MASK;
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}
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static bool sun50i_dte_is_pt_valid(u32 dte)
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{
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return (dte & SUN50I_DTE_PT_ATTRS) == SUN50I_DTE_PT_VALID;
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}
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static u32 sun50i_mk_dte(dma_addr_t pt_dma)
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{
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return (pt_dma & SUN50I_DTE_PT_ADDRESS_MASK) | SUN50I_DTE_PT_VALID;
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}
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/*
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* Each PTE has a Page address, an authority index and a valid bit:
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*
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* +----------------+-----+-----+-----+---+-----+
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* | Page address | Rsv | ACI | Rsv | V | Rsv |
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* +----------------+-----+-----+-----+---+-----+
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* 31:12 - Page address
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* 11:8 - Reserved
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* 7:4 - Authority Control Index
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* 3:2 - Reserved
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* 1 - 1 if the entry is valid
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* 0 - Reserved
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*
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* The way permissions work is that the IOMMU has 16 "domains" that
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* can be configured to give each masters either read or write
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* permissions through the IOMMU_DM_AUT_CTRL_REG registers. The domain
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* 0 seems like the default domain, and its permissions in the
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* IOMMU_DM_AUT_CTRL_REG are only read-only, so it's not really
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* useful to enforce any particular permission.
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*
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* Each page entry will then have a reference to the domain they are
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* affected to, so that we can actually enforce them on a per-page
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* basis.
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*
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* In order to make it work with the IOMMU framework, we will be using
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* 4 different domains, starting at 1: RD_WR, RD, WR and NONE
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* depending on the permission we want to enforce. Each domain will
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* have each master setup in the same way, since the IOMMU framework
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* doesn't seem to restrict page access on a per-device basis. And
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* then we will use the relevant domain index when generating the page
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* table entry depending on the permissions we want to be enforced.
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*/
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enum sun50i_iommu_aci {
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SUN50I_IOMMU_ACI_DO_NOT_USE = 0,
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SUN50I_IOMMU_ACI_NONE,
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SUN50I_IOMMU_ACI_RD,
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SUN50I_IOMMU_ACI_WR,
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SUN50I_IOMMU_ACI_RD_WR,
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};
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#define SUN50I_PTE_PAGE_ADDRESS_MASK GENMASK(31, 12)
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#define SUN50I_PTE_ACI_MASK GENMASK(7, 4)
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#define SUN50I_PTE_PAGE_VALID BIT(1)
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static phys_addr_t sun50i_pte_get_page_address(u32 pte)
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{
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return (phys_addr_t)pte & SUN50I_PTE_PAGE_ADDRESS_MASK;
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}
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static enum sun50i_iommu_aci sun50i_get_pte_aci(u32 pte)
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{
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return FIELD_GET(SUN50I_PTE_ACI_MASK, pte);
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}
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static bool sun50i_pte_is_page_valid(u32 pte)
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{
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return pte & SUN50I_PTE_PAGE_VALID;
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}
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static u32 sun50i_mk_pte(phys_addr_t page, int prot)
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{
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enum sun50i_iommu_aci aci;
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u32 flags = 0;
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if (prot & (IOMMU_READ | IOMMU_WRITE))
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aci = SUN50I_IOMMU_ACI_RD_WR;
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else if (prot & IOMMU_READ)
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aci = SUN50I_IOMMU_ACI_RD;
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else if (prot & IOMMU_WRITE)
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aci = SUN50I_IOMMU_ACI_WR;
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else
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aci = SUN50I_IOMMU_ACI_NONE;
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flags |= FIELD_PREP(SUN50I_PTE_ACI_MASK, aci);
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page &= SUN50I_PTE_PAGE_ADDRESS_MASK;
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return page | flags | SUN50I_PTE_PAGE_VALID;
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}
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static void sun50i_table_flush(struct sun50i_iommu_domain *sun50i_domain,
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void *vaddr, unsigned int count)
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{
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struct sun50i_iommu *iommu = sun50i_domain->iommu;
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dma_addr_t dma = virt_to_phys(vaddr);
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size_t size = count * PT_ENTRY_SIZE;
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dma_sync_single_for_device(iommu->dev, dma, size, DMA_TO_DEVICE);
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}
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static int sun50i_iommu_flush_all_tlb(struct sun50i_iommu *iommu)
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{
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u32 reg;
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int ret;
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assert_spin_locked(&iommu->iommu_lock);
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iommu_write(iommu,
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IOMMU_TLB_FLUSH_REG,
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IOMMU_TLB_FLUSH_PTW_CACHE |
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IOMMU_TLB_FLUSH_MACRO_TLB |
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IOMMU_TLB_FLUSH_MICRO_TLB(5) |
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IOMMU_TLB_FLUSH_MICRO_TLB(4) |
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IOMMU_TLB_FLUSH_MICRO_TLB(3) |
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IOMMU_TLB_FLUSH_MICRO_TLB(2) |
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IOMMU_TLB_FLUSH_MICRO_TLB(1) |
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IOMMU_TLB_FLUSH_MICRO_TLB(0));
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ret = readl_poll_timeout(iommu->base + IOMMU_TLB_FLUSH_REG,
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reg, !reg,
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1, 2000);
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if (ret)
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dev_warn(iommu->dev, "TLB Flush timed out!\n");
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return ret;
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}
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static void sun50i_iommu_flush_iotlb_all(struct iommu_domain *domain)
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{
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struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
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struct sun50i_iommu *iommu = sun50i_domain->iommu;
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unsigned long flags;
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/*
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* At boot, we'll have a first call into .flush_iotlb_all right after
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* .probe_device, and since we link our (single) domain to our iommu in
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* the .attach_device callback, we don't have that pointer set.
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*
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* It shouldn't really be any trouble to ignore it though since we flush
|
|
|
|
* all caches as part of the device powerup.
|
|
|
|
*/
|
|
|
|
if (!iommu)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->iommu_lock, flags);
|
|
|
|
sun50i_iommu_flush_all_tlb(iommu);
|
|
|
|
spin_unlock_irqrestore(&iommu->iommu_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_iotlb_sync(struct iommu_domain *domain,
|
|
|
|
struct iommu_iotlb_gather *gather)
|
|
|
|
{
|
|
|
|
sun50i_iommu_flush_iotlb_all(domain);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!iommu->domain)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
sun50i_domain = to_sun50i_domain(iommu->domain);
|
|
|
|
|
|
|
|
ret = reset_control_deassert(iommu->reset);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(iommu->clk);
|
|
|
|
if (ret)
|
|
|
|
goto err_reset_assert;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->iommu_lock, flags);
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
|
|
|
|
iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(1) |
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(2) |
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(3) |
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(4) |
|
|
|
|
IOMMU_TLB_PREFETCH_MASTER_ENABLE(5));
|
|
|
|
iommu_write(iommu, IOMMU_INT_ENABLE_REG, IOMMU_INT_MASK);
|
|
|
|
iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_NONE),
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 1) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 1) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 2) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 2) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 3) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 3) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 4) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 4) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 5) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 5));
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_RD),
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 0) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 1) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 2) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 3) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 4) |
|
|
|
|
IOMMU_DM_AUT_CTRL_WR_UNAVAIL(SUN50I_IOMMU_ACI_RD, 5));
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_WR),
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 0) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 1) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 2) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 3) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 4) |
|
|
|
|
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_WR, 5));
|
|
|
|
|
|
|
|
ret = sun50i_iommu_flush_all_tlb(iommu);
|
|
|
|
if (ret) {
|
|
|
|
spin_unlock_irqrestore(&iommu->iommu_lock, flags);
|
|
|
|
goto err_clk_disable;
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_AUTO_GATING_REG, IOMMU_AUTO_GATING_ENABLE);
|
|
|
|
iommu_write(iommu, IOMMU_ENABLE_REG, IOMMU_ENABLE_ENABLE);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->iommu_lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_clk_disable:
|
|
|
|
clk_disable_unprepare(iommu->clk);
|
|
|
|
|
|
|
|
err_reset_assert:
|
|
|
|
reset_control_assert(iommu->reset);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_disable(struct sun50i_iommu *iommu)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->iommu_lock, flags);
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_ENABLE_REG, 0);
|
|
|
|
iommu_write(iommu, IOMMU_TTB_REG, 0);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->iommu_lock, flags);
|
|
|
|
|
|
|
|
clk_disable_unprepare(iommu->clk);
|
|
|
|
reset_control_assert(iommu->reset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *sun50i_iommu_alloc_page_table(struct sun50i_iommu *iommu,
|
|
|
|
gfp_t gfp)
|
|
|
|
{
|
|
|
|
dma_addr_t pt_dma;
|
|
|
|
u32 *page_table;
|
|
|
|
|
|
|
|
page_table = kmem_cache_zalloc(iommu->pt_pool, gfp);
|
|
|
|
if (!page_table)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
pt_dma = dma_map_single(iommu->dev, page_table, PT_SIZE, DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(iommu->dev, pt_dma)) {
|
|
|
|
dev_err(iommu->dev, "Couldn't map L2 Page Table\n");
|
|
|
|
kmem_cache_free(iommu->pt_pool, page_table);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We rely on the physical address and DMA address being the same */
|
|
|
|
WARN_ON(pt_dma != virt_to_phys(page_table));
|
|
|
|
|
|
|
|
return page_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_free_page_table(struct sun50i_iommu *iommu,
|
|
|
|
u32 *page_table)
|
|
|
|
{
|
|
|
|
phys_addr_t pt_phys = virt_to_phys(page_table);
|
|
|
|
|
|
|
|
dma_unmap_single(iommu->dev, pt_phys, PT_SIZE, DMA_TO_DEVICE);
|
|
|
|
kmem_cache_free(iommu->pt_pool, page_table);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 *sun50i_dte_get_page_table(struct sun50i_iommu_domain *sun50i_domain,
|
|
|
|
dma_addr_t iova, gfp_t gfp)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu *iommu = sun50i_domain->iommu;
|
|
|
|
u32 *page_table;
|
|
|
|
u32 *dte_addr;
|
|
|
|
u32 old_dte;
|
|
|
|
u32 dte;
|
|
|
|
|
|
|
|
dte_addr = &sun50i_domain->dt[sun50i_iova_get_dte_index(iova)];
|
|
|
|
dte = *dte_addr;
|
|
|
|
if (sun50i_dte_is_pt_valid(dte)) {
|
|
|
|
phys_addr_t pt_phys = sun50i_dte_get_pt_address(dte);
|
|
|
|
return (u32 *)phys_to_virt(pt_phys);
|
|
|
|
}
|
|
|
|
|
|
|
|
page_table = sun50i_iommu_alloc_page_table(iommu, gfp);
|
|
|
|
if (IS_ERR(page_table))
|
|
|
|
return page_table;
|
|
|
|
|
|
|
|
dte = sun50i_mk_dte(virt_to_phys(page_table));
|
|
|
|
old_dte = cmpxchg(dte_addr, 0, dte);
|
|
|
|
if (old_dte) {
|
|
|
|
phys_addr_t installed_pt_phys =
|
|
|
|
sun50i_dte_get_pt_address(old_dte);
|
|
|
|
u32 *installed_pt = phys_to_virt(installed_pt_phys);
|
|
|
|
u32 *drop_pt = page_table;
|
|
|
|
|
|
|
|
page_table = installed_pt;
|
|
|
|
dte = old_dte;
|
|
|
|
sun50i_iommu_free_page_table(iommu, drop_pt);
|
|
|
|
}
|
|
|
|
|
|
|
|
sun50i_table_flush(sun50i_domain, page_table, PT_SIZE);
|
|
|
|
sun50i_table_flush(sun50i_domain, dte_addr, 1);
|
|
|
|
|
|
|
|
return page_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
|
|
|
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
struct sun50i_iommu *iommu = sun50i_domain->iommu;
|
|
|
|
u32 pte_index;
|
|
|
|
u32 *page_table, *pte_addr;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp);
|
|
|
|
if (IS_ERR(page_table)) {
|
|
|
|
ret = PTR_ERR(page_table);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
pte_index = sun50i_iova_get_pte_index(iova);
|
|
|
|
pte_addr = &page_table[pte_index];
|
|
|
|
if (unlikely(sun50i_pte_is_page_valid(*pte_addr))) {
|
|
|
|
phys_addr_t page_phys = sun50i_pte_get_page_address(*pte_addr);
|
|
|
|
dev_err(iommu->dev,
|
|
|
|
"iova %pad already mapped to %pa cannot remap to %pa prot: %#x\n",
|
|
|
|
&iova, &page_phys, &paddr, prot);
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
*pte_addr = sun50i_mk_pte(paddr, prot);
|
|
|
|
sun50i_table_flush(sun50i_domain, pte_addr, 1);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|
|
|
size_t size, struct iommu_iotlb_gather *gather)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
phys_addr_t pt_phys;
|
|
|
|
dma_addr_t pte_dma;
|
|
|
|
u32 *pte_addr;
|
|
|
|
u32 dte;
|
|
|
|
|
|
|
|
dte = sun50i_domain->dt[sun50i_iova_get_dte_index(iova)];
|
|
|
|
if (!sun50i_dte_is_pt_valid(dte))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pt_phys = sun50i_dte_get_pt_address(dte);
|
|
|
|
pte_addr = (u32 *)phys_to_virt(pt_phys) + sun50i_iova_get_pte_index(iova);
|
|
|
|
pte_dma = pt_phys + sun50i_iova_get_pte_index(iova) * PT_ENTRY_SIZE;
|
|
|
|
|
|
|
|
if (!sun50i_pte_is_page_valid(*pte_addr))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
memset(pte_addr, 0, sizeof(*pte_addr));
|
|
|
|
sun50i_table_flush(sun50i_domain, pte_addr, 1);
|
|
|
|
|
|
|
|
return SZ_4K;
|
|
|
|
}
|
|
|
|
|
|
|
|
static phys_addr_t sun50i_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
|
|
dma_addr_t iova)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
phys_addr_t pt_phys;
|
|
|
|
u32 *page_table;
|
|
|
|
u32 dte, pte;
|
|
|
|
|
|
|
|
dte = sun50i_domain->dt[sun50i_iova_get_dte_index(iova)];
|
|
|
|
if (!sun50i_dte_is_pt_valid(dte))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pt_phys = sun50i_dte_get_pt_address(dte);
|
|
|
|
page_table = (u32 *)phys_to_virt(pt_phys);
|
|
|
|
pte = page_table[sun50i_iova_get_pte_index(iova)];
|
|
|
|
if (!sun50i_pte_is_page_valid(pte))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return sun50i_pte_get_page_address(pte) +
|
|
|
|
sun50i_iova_get_page_offset(iova);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct iommu_domain *sun50i_iommu_domain_alloc(unsigned type)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain;
|
|
|
|
|
|
|
|
if (type != IOMMU_DOMAIN_DMA &&
|
|
|
|
type != IOMMU_DOMAIN_IDENTITY &&
|
|
|
|
type != IOMMU_DOMAIN_UNMANAGED)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
sun50i_domain = kzalloc(sizeof(*sun50i_domain), GFP_KERNEL);
|
|
|
|
if (!sun50i_domain)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (type == IOMMU_DOMAIN_DMA &&
|
|
|
|
iommu_get_dma_cookie(&sun50i_domain->domain))
|
|
|
|
goto err_free_domain;
|
|
|
|
|
2020-05-14 06:46:21 -06:00
|
|
|
sun50i_domain->dt = (u32 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
2020-05-13 08:07:22 -06:00
|
|
|
get_order(DT_SIZE));
|
|
|
|
if (!sun50i_domain->dt)
|
|
|
|
goto err_put_cookie;
|
|
|
|
|
|
|
|
refcount_set(&sun50i_domain->refcnt, 1);
|
|
|
|
|
|
|
|
sun50i_domain->domain.geometry.aperture_start = 0;
|
|
|
|
sun50i_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
|
|
|
|
sun50i_domain->domain.geometry.force_aperture = true;
|
|
|
|
|
|
|
|
return &sun50i_domain->domain;
|
|
|
|
|
|
|
|
err_put_cookie:
|
|
|
|
if (type == IOMMU_DOMAIN_DMA)
|
|
|
|
iommu_put_dma_cookie(&sun50i_domain->domain);
|
|
|
|
|
|
|
|
err_free_domain:
|
|
|
|
kfree(sun50i_domain);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_domain_free(struct iommu_domain *domain)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
|
|
|
|
free_pages((unsigned long)sun50i_domain->dt, get_order(DT_SIZE));
|
|
|
|
sun50i_domain->dt = NULL;
|
|
|
|
|
|
|
|
iommu_put_dma_cookie(domain);
|
|
|
|
|
|
|
|
kfree(sun50i_domain);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_attach_domain(struct sun50i_iommu *iommu,
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain)
|
|
|
|
{
|
|
|
|
iommu->domain = &sun50i_domain->domain;
|
|
|
|
sun50i_domain->iommu = iommu;
|
|
|
|
|
|
|
|
sun50i_domain->dt_dma = dma_map_single(iommu->dev, sun50i_domain->dt,
|
|
|
|
DT_SIZE, DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(iommu->dev, sun50i_domain->dt_dma)) {
|
|
|
|
dev_err(iommu->dev, "Couldn't map L1 Page Table\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return sun50i_iommu_enable(iommu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_detach_domain(struct sun50i_iommu *iommu,
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_DT_ENTRIES; i++) {
|
|
|
|
phys_addr_t pt_phys;
|
|
|
|
u32 *page_table;
|
|
|
|
u32 *dte_addr;
|
|
|
|
u32 dte;
|
|
|
|
|
|
|
|
dte_addr = &sun50i_domain->dt[i];
|
|
|
|
dte = *dte_addr;
|
|
|
|
if (!sun50i_dte_is_pt_valid(dte))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
memset(dte_addr, 0, sizeof(*dte_addr));
|
|
|
|
sun50i_table_flush(sun50i_domain, dte_addr, 1);
|
|
|
|
|
|
|
|
pt_phys = sun50i_dte_get_pt_address(dte);
|
|
|
|
page_table = phys_to_virt(pt_phys);
|
|
|
|
sun50i_iommu_free_page_table(iommu, page_table);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
sun50i_iommu_disable(iommu);
|
|
|
|
|
|
|
|
dma_unmap_single(iommu->dev, virt_to_phys(sun50i_domain->dt),
|
|
|
|
DT_SIZE, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
iommu->domain = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_detach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
struct sun50i_iommu *iommu = dev_iommu_priv_get(dev);
|
|
|
|
|
|
|
|
dev_dbg(dev, "Detaching from IOMMU domain\n");
|
|
|
|
|
|
|
|
if (iommu->domain != domain)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (refcount_dec_and_test(&sun50i_domain->refcnt))
|
|
|
|
sun50i_iommu_detach_domain(iommu, sun50i_domain);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_attach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
|
|
|
|
struct sun50i_iommu *iommu;
|
|
|
|
|
|
|
|
iommu = sun50i_iommu_from_dev(dev);
|
|
|
|
if (!iommu)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
dev_dbg(dev, "Attaching to IOMMU domain\n");
|
|
|
|
|
|
|
|
refcount_inc(&sun50i_domain->refcnt);
|
|
|
|
|
|
|
|
if (iommu->domain == domain)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (iommu->domain)
|
|
|
|
sun50i_iommu_detach_device(iommu->domain, dev);
|
|
|
|
|
|
|
|
sun50i_iommu_attach_domain(iommu, sun50i_domain);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct iommu_device *sun50i_iommu_probe_device(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu *iommu;
|
|
|
|
|
|
|
|
iommu = sun50i_iommu_from_dev(dev);
|
|
|
|
if (!iommu)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
return &iommu->iommu;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun50i_iommu_release_device(struct device *dev) {}
|
|
|
|
|
|
|
|
static struct iommu_group *sun50i_iommu_device_group(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu *iommu = sun50i_iommu_from_dev(dev);
|
|
|
|
|
|
|
|
return iommu_group_ref_get(iommu->group);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_of_xlate(struct device *dev,
|
|
|
|
struct of_phandle_args *args)
|
|
|
|
{
|
|
|
|
struct platform_device *iommu_pdev = of_find_device_by_node(args->np);
|
|
|
|
unsigned id = args->args[0];
|
|
|
|
|
|
|
|
dev_iommu_priv_set(dev, platform_get_drvdata(iommu_pdev));
|
|
|
|
|
|
|
|
return iommu_fwspec_add_ids(dev, &id, 1);
|
|
|
|
}
|
|
|
|
|
2020-05-25 15:49:58 -06:00
|
|
|
static const struct iommu_ops sun50i_iommu_ops = {
|
2020-05-13 08:07:22 -06:00
|
|
|
.pgsize_bitmap = SZ_4K,
|
|
|
|
.attach_dev = sun50i_iommu_attach_device,
|
|
|
|
.detach_dev = sun50i_iommu_detach_device,
|
|
|
|
.device_group = sun50i_iommu_device_group,
|
|
|
|
.domain_alloc = sun50i_iommu_domain_alloc,
|
|
|
|
.domain_free = sun50i_iommu_domain_free,
|
|
|
|
.flush_iotlb_all = sun50i_iommu_flush_iotlb_all,
|
|
|
|
.iotlb_sync = sun50i_iommu_iotlb_sync,
|
|
|
|
.iova_to_phys = sun50i_iommu_iova_to_phys,
|
|
|
|
.map = sun50i_iommu_map,
|
|
|
|
.of_xlate = sun50i_iommu_of_xlate,
|
|
|
|
.probe_device = sun50i_iommu_probe_device,
|
|
|
|
.release_device = sun50i_iommu_release_device,
|
|
|
|
.unmap = sun50i_iommu_unmap,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void sun50i_iommu_report_fault(struct sun50i_iommu *iommu,
|
|
|
|
unsigned master, phys_addr_t iova,
|
|
|
|
unsigned prot)
|
|
|
|
{
|
|
|
|
dev_err(iommu->dev, "Page fault for %pad (master %d, dir %s)\n",
|
|
|
|
&iova, master, (prot == IOMMU_FAULT_WRITE) ? "wr" : "rd");
|
|
|
|
|
|
|
|
if (iommu->domain)
|
|
|
|
report_iommu_fault(iommu->domain, iommu->dev, iova, prot);
|
|
|
|
else
|
|
|
|
dev_err(iommu->dev, "Page fault while iommu not attached to any domain?\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static phys_addr_t sun50i_iommu_handle_pt_irq(struct sun50i_iommu *iommu,
|
|
|
|
unsigned addr_reg,
|
|
|
|
unsigned blame_reg)
|
|
|
|
{
|
|
|
|
phys_addr_t iova;
|
|
|
|
unsigned master;
|
|
|
|
u32 blame;
|
|
|
|
|
|
|
|
assert_spin_locked(&iommu->iommu_lock);
|
|
|
|
|
|
|
|
iova = iommu_read(iommu, addr_reg);
|
|
|
|
blame = iommu_read(iommu, blame_reg);
|
|
|
|
master = ilog2(blame & IOMMU_INT_MASTER_MASK);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the address is not in the page table, we can't get what
|
|
|
|
* operation triggered the fault. Assume it's a read
|
|
|
|
* operation.
|
|
|
|
*/
|
|
|
|
sun50i_iommu_report_fault(iommu, master, iova, IOMMU_FAULT_READ);
|
|
|
|
|
|
|
|
return iova;
|
|
|
|
}
|
|
|
|
|
|
|
|
static phys_addr_t sun50i_iommu_handle_perm_irq(struct sun50i_iommu *iommu)
|
|
|
|
{
|
|
|
|
enum sun50i_iommu_aci aci;
|
|
|
|
phys_addr_t iova;
|
|
|
|
unsigned master;
|
|
|
|
unsigned dir;
|
|
|
|
u32 blame;
|
|
|
|
|
|
|
|
assert_spin_locked(&iommu->iommu_lock);
|
|
|
|
|
|
|
|
blame = iommu_read(iommu, IOMMU_INT_STA_REG);
|
|
|
|
master = ilog2(blame & IOMMU_INT_MASTER_MASK);
|
|
|
|
iova = iommu_read(iommu, IOMMU_INT_ERR_ADDR_REG(master));
|
|
|
|
aci = sun50i_get_pte_aci(iommu_read(iommu,
|
|
|
|
IOMMU_INT_ERR_DATA_REG(master)));
|
|
|
|
|
|
|
|
switch (aci) {
|
|
|
|
/*
|
|
|
|
* If we are in the read-only domain, then it means we
|
|
|
|
* tried to write.
|
|
|
|
*/
|
|
|
|
case SUN50I_IOMMU_ACI_RD:
|
|
|
|
dir = IOMMU_FAULT_WRITE;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are in the write-only domain, then it means
|
|
|
|
* we tried to read.
|
|
|
|
*/
|
|
|
|
case SUN50I_IOMMU_ACI_WR:
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are in the domain without any permission, we
|
|
|
|
* can't really tell. Let's default to a read
|
|
|
|
* operation.
|
|
|
|
*/
|
|
|
|
case SUN50I_IOMMU_ACI_NONE:
|
|
|
|
|
|
|
|
/* WTF? */
|
|
|
|
case SUN50I_IOMMU_ACI_RD_WR:
|
|
|
|
default:
|
|
|
|
dir = IOMMU_FAULT_READ;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the address is not in the page table, we can't get what
|
|
|
|
* operation triggered the fault. Assume it's a read
|
|
|
|
* operation.
|
|
|
|
*/
|
|
|
|
sun50i_iommu_report_fault(iommu, master, iova, dir);
|
|
|
|
|
|
|
|
return iova;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu *iommu = dev_id;
|
|
|
|
phys_addr_t iova;
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
spin_lock(&iommu->iommu_lock);
|
|
|
|
|
|
|
|
status = iommu_read(iommu, IOMMU_INT_STA_REG);
|
|
|
|
if (!(status & IOMMU_INT_MASK)) {
|
|
|
|
spin_unlock(&iommu->iommu_lock);
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & IOMMU_INT_INVALID_L2PG)
|
|
|
|
iova = sun50i_iommu_handle_pt_irq(iommu,
|
|
|
|
IOMMU_INT_ERR_ADDR_L2_REG,
|
|
|
|
IOMMU_L2PG_INT_REG);
|
|
|
|
else if (status & IOMMU_INT_INVALID_L1PG)
|
|
|
|
iova = sun50i_iommu_handle_pt_irq(iommu,
|
|
|
|
IOMMU_INT_ERR_ADDR_L1_REG,
|
|
|
|
IOMMU_L1PG_INT_REG);
|
|
|
|
else
|
|
|
|
iova = sun50i_iommu_handle_perm_irq(iommu);
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_INT_CLR_REG, status);
|
|
|
|
|
|
|
|
iommu_write(iommu, IOMMU_RESET_REG, ~status);
|
|
|
|
iommu_write(iommu, IOMMU_RESET_REG, status);
|
|
|
|
|
|
|
|
spin_unlock(&iommu->iommu_lock);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun50i_iommu_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct sun50i_iommu *iommu;
|
|
|
|
int ret, irq;
|
|
|
|
|
|
|
|
iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
|
|
|
|
if (!iommu)
|
|
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&iommu->iommu_lock);
|
|
|
|
platform_set_drvdata(pdev, iommu);
|
|
|
|
iommu->dev = &pdev->dev;
|
|
|
|
|
|
|
|
iommu->pt_pool = kmem_cache_create(dev_name(&pdev->dev),
|
|
|
|
PT_SIZE, PT_SIZE,
|
|
|
|
SLAB_HWCACHE_ALIGN,
|
|
|
|
NULL);
|
|
|
|
if (!iommu->pt_pool)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
iommu->group = iommu_group_alloc();
|
|
|
|
if (IS_ERR(iommu->group)) {
|
|
|
|
ret = PTR_ERR(iommu->group);
|
|
|
|
goto err_free_cache;
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu->base = devm_platform_ioremap_resource(pdev, 0);
|
2020-05-19 03:18:57 -06:00
|
|
|
if (IS_ERR(iommu->base)) {
|
2020-05-13 08:07:22 -06:00
|
|
|
ret = PTR_ERR(iommu->base);
|
|
|
|
goto err_free_group;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
|
|
|
goto err_free_group;
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(iommu->clk)) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't get our clock.\n");
|
|
|
|
ret = PTR_ERR(iommu->clk);
|
|
|
|
goto err_free_group;
|
|
|
|
}
|
|
|
|
|
|
|
|
iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(iommu->reset)) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't get our reset line.\n");
|
|
|
|
ret = PTR_ERR(iommu->reset);
|
|
|
|
goto err_free_group;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = iommu_device_sysfs_add(&iommu->iommu, &pdev->dev,
|
|
|
|
NULL, dev_name(&pdev->dev));
|
|
|
|
if (ret)
|
|
|
|
goto err_free_group;
|
|
|
|
|
|
|
|
iommu_device_set_ops(&iommu->iommu, &sun50i_iommu_ops);
|
|
|
|
iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);
|
|
|
|
|
|
|
|
ret = iommu_device_register(&iommu->iommu);
|
|
|
|
if (ret)
|
|
|
|
goto err_remove_sysfs;
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, sun50i_iommu_irq, 0,
|
|
|
|
dev_name(&pdev->dev), iommu);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_unregister;
|
|
|
|
|
|
|
|
bus_set_iommu(&platform_bus_type, &sun50i_iommu_ops);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unregister:
|
|
|
|
iommu_device_unregister(&iommu->iommu);
|
|
|
|
|
|
|
|
err_remove_sysfs:
|
|
|
|
iommu_device_sysfs_remove(&iommu->iommu);
|
|
|
|
|
|
|
|
err_free_group:
|
|
|
|
iommu_group_put(iommu->group);
|
|
|
|
|
|
|
|
err_free_cache:
|
|
|
|
kmem_cache_destroy(iommu->pt_pool);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id sun50i_iommu_dt[] = {
|
|
|
|
{ .compatible = "allwinner,sun50i-h6-iommu", },
|
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sun50i_iommu_dt);
|
|
|
|
|
|
|
|
static struct platform_driver sun50i_iommu_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "sun50i-iommu",
|
|
|
|
.of_match_table = sun50i_iommu_dt,
|
|
|
|
.suppress_bind_attrs = true,
|
|
|
|
}
|
|
|
|
};
|
|
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builtin_platform_driver_probe(sun50i_iommu_driver, sun50i_iommu_probe);
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MODULE_DESCRIPTION("Allwinner H6 IOMMU driver");
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MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>");
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MODULE_AUTHOR("zhuxianbin <zhuxianbin@allwinnertech.com>");
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MODULE_LICENSE("Dual BSD/GPL");
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