2005-04-16 16:20:36 -06:00
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/*
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* Basic EISA bus support for the SGI Indigo-2.
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*
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* (C) 2002 Pascal Dameme <netinet@freesurf.fr>
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* and Marc Zyngier <mzyngier@freesurf.fr>
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*
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* This code is released under both the GPL version 2 and BSD
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* licenses. Either license may be used.
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*
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* This code offers a very basic support for this EISA bus present in
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* the SGI Indigo-2. It currently only supports PIO (forget about DMA
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* for the time being). This is enough for a low-end ethernet card,
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* but forget about your favorite SCSI card...
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*
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* TODO :
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* - Fix bugs...
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* - Add ISA support
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* - Add DMA (yeah, right...).
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* - Fix more bugs.
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*/
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#include <linux/eisa.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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2005-08-31 09:55:16 -06:00
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#include <asm/io.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/processor.h>
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#include <asm/sgi/ioc.h>
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#include <asm/sgi/mc.h>
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#include <asm/sgi/ip22.h>
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2005-08-31 09:55:16 -06:00
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/* I2 has four EISA slots. */
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#define IP22_EISA_MAX_SLOTS 4
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2005-04-16 16:20:36 -06:00
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#define EISA_MAX_IRQ 16
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2005-08-31 09:55:16 -06:00
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#define EIU_MODE_REG 0x0001ffc0
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#define EIU_STAT_REG 0x0001ffc4
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#define EIU_PREMPT_REG 0x0001ffc8
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#define EIU_QUIET_REG 0x0001ffcc
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#define EIU_INTRPT_ACK 0x00010004
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static char __init *decode_eisa_sig(unsigned long addr)
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2005-04-16 16:20:36 -06:00
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{
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2005-08-31 09:55:16 -06:00
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static char sig_str[EISA_SIG_LEN];
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u8 sig[4];
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u16 rev;
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int i;
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for (i = 0; i < 4; i++) {
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sig[i] = inb (addr + i);
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2005-04-16 16:20:36 -06:00
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2005-08-31 09:55:16 -06:00
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if (!i && (sig[0] & 0x80))
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return NULL;
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}
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2005-04-16 16:20:36 -06:00
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sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
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sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
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sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
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rev = (sig[2] << 8) | sig[3];
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sprintf(sig_str + 3, "%04X", rev);
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return sig_str;
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}
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2006-10-07 12:44:33 -06:00
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static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
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2005-04-16 16:20:36 -06:00
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{
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u8 eisa_irq;
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u8 dma1, dma2;
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2005-08-31 09:55:16 -06:00
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eisa_irq = inb(EIU_INTRPT_ACK);
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dma1 = inb(EISA_DMA1_STATUS);
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dma2 = inb(EISA_DMA2_STATUS);
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2005-04-16 16:20:36 -06:00
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2005-08-31 09:55:16 -06:00
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if (eisa_irq < EISA_MAX_IRQ) {
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2006-10-07 12:44:33 -06:00
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do_IRQ(eisa_irq);
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2005-08-31 09:55:16 -06:00
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return IRQ_HANDLED;
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}
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/* Oops, Bad Stuff Happened... */
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printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
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outb(0x20, EISA_INT2_CTRL);
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outb(0x20, EISA_INT1_CTRL);
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2006-10-07 12:44:33 -06:00
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2005-08-31 09:55:16 -06:00
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return IRQ_NONE;
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2005-04-16 16:20:36 -06:00
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}
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static void enable_eisa1_irq(unsigned int irq)
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{
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unsigned long flags;
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u8 mask;
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local_irq_save(flags);
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2005-08-31 09:55:16 -06:00
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mask = inb(EISA_INT1_MASK);
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2005-04-16 16:20:36 -06:00
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mask &= ~((u8) (1 << irq));
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2005-08-31 09:55:16 -06:00
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outb(mask, EISA_INT1_MASK);
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2005-04-16 16:20:36 -06:00
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local_irq_restore(flags);
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}
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static unsigned int startup_eisa1_irq(unsigned int irq)
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{
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u8 edge;
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/* Only use edge interrupts for EISA */
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2005-08-31 09:55:16 -06:00
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edge = inb(EISA_INT1_EDGE_LEVEL);
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2005-04-16 16:20:36 -06:00
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edge &= ~((u8) (1 << irq));
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2005-08-31 09:55:16 -06:00
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outb(edge, EISA_INT1_EDGE_LEVEL);
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2005-04-16 16:20:36 -06:00
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enable_eisa1_irq(irq);
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return 0;
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}
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static void disable_eisa1_irq(unsigned int irq)
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{
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u8 mask;
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2005-08-31 09:55:16 -06:00
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mask = inb(EISA_INT1_MASK);
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2005-04-16 16:20:36 -06:00
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mask |= ((u8) (1 << irq));
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2005-08-31 09:55:16 -06:00
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outb(mask, EISA_INT1_MASK);
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2005-04-16 16:20:36 -06:00
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}
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#define shutdown_eisa1_irq disable_eisa1_irq
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static void mask_and_ack_eisa1_irq(unsigned int irq)
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{
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disable_eisa1_irq(irq);
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2005-08-31 09:55:16 -06:00
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outb(0x20, EISA_INT1_CTRL);
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2005-04-16 16:20:36 -06:00
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}
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static void end_eisa1_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_eisa1_irq(irq);
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}
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2006-07-02 07:41:42 -06:00
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static struct irq_chip ip22_eisa1_irq_type = {
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2005-04-16 16:20:36 -06:00
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.typename = "IP22 EISA",
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.startup = startup_eisa1_irq,
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.shutdown = shutdown_eisa1_irq,
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.enable = enable_eisa1_irq,
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.disable = disable_eisa1_irq,
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.ack = mask_and_ack_eisa1_irq,
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.end = end_eisa1_irq,
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};
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static void enable_eisa2_irq(unsigned int irq)
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{
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unsigned long flags;
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u8 mask;
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local_irq_save(flags);
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2005-08-31 09:55:16 -06:00
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mask = inb(EISA_INT2_MASK);
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2005-04-16 16:20:36 -06:00
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mask &= ~((u8) (1 << (irq - 8)));
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2005-08-31 09:55:16 -06:00
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outb(mask, EISA_INT2_MASK);
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2005-04-16 16:20:36 -06:00
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local_irq_restore(flags);
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}
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static unsigned int startup_eisa2_irq(unsigned int irq)
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{
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u8 edge;
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/* Only use edge interrupts for EISA */
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2005-08-31 09:55:16 -06:00
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edge = inb(EISA_INT2_EDGE_LEVEL);
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2005-04-16 16:20:36 -06:00
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edge &= ~((u8) (1 << (irq - 8)));
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2005-08-31 09:55:16 -06:00
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outb(edge, EISA_INT2_EDGE_LEVEL);
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2005-04-16 16:20:36 -06:00
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enable_eisa2_irq(irq);
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return 0;
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}
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static void disable_eisa2_irq(unsigned int irq)
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{
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u8 mask;
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2005-08-31 09:55:16 -06:00
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mask = inb(EISA_INT2_MASK);
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2005-04-16 16:20:36 -06:00
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mask |= ((u8) (1 << (irq - 8)));
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2005-08-31 09:55:16 -06:00
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outb(mask, EISA_INT2_MASK);
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2005-04-16 16:20:36 -06:00
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}
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#define shutdown_eisa2_irq disable_eisa2_irq
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static void mask_and_ack_eisa2_irq(unsigned int irq)
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{
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disable_eisa2_irq(irq);
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2005-08-31 09:55:16 -06:00
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outb(0x20, EISA_INT2_CTRL);
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2005-04-16 16:20:36 -06:00
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}
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static void end_eisa2_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_eisa2_irq(irq);
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}
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2006-07-02 07:41:42 -06:00
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static struct irq_chip ip22_eisa2_irq_type = {
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2005-04-16 16:20:36 -06:00
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.typename = "IP22 EISA",
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.startup = startup_eisa2_irq,
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.shutdown = shutdown_eisa2_irq,
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.enable = enable_eisa2_irq,
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.disable = disable_eisa2_irq,
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.ack = mask_and_ack_eisa2_irq,
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.end = end_eisa2_irq,
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};
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static struct irqaction eisa_action = {
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.handler = ip22_eisa_intr,
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.name = "EISA",
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};
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static struct irqaction cascade_action = {
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.handler = no_action,
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.name = "EISA cascade",
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};
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int __init ip22_eisa_init(void)
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{
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int i, c;
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char *str;
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2005-09-03 16:56:17 -06:00
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2005-04-16 16:20:36 -06:00
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if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
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printk(KERN_INFO "EISA: bus not present.\n");
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return 1;
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}
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printk(KERN_INFO "EISA: Probing bus...\n");
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2005-08-31 09:55:16 -06:00
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for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
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if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
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2005-04-16 16:20:36 -06:00
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printk(KERN_INFO "EISA: slot %d : %s detected.\n",
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i, str);
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c++;
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}
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}
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printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
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#ifdef CONFIG_ISA
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printk(KERN_INFO "ISA support compiled in.\n");
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#endif
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/* Warning : BlackMagicAhead(tm).
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Please wave your favorite dead chicken over the busses */
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/* First say hello to the EIU */
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2005-08-31 09:55:16 -06:00
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outl(0x0000FFFF, EIU_PREMPT_REG);
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outl(1, EIU_QUIET_REG);
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outl(0x40f3c07F, EIU_MODE_REG);
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2005-04-16 16:20:36 -06:00
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/* Now be nice to the EISA chipset */
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2005-08-31 09:55:16 -06:00
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outb(1, EISA_EXT_NMI_RESET_CTRL);
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udelay(50); /* Wait long enough for the dust to settle */
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outb(0, EISA_EXT_NMI_RESET_CTRL);
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outb(0x11, EISA_INT1_CTRL);
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outb(0x11, EISA_INT2_CTRL);
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outb(0, EISA_INT1_MASK);
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outb(8, EISA_INT2_MASK);
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outb(4, EISA_INT1_MASK);
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outb(2, EISA_INT2_MASK);
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outb(1, EISA_INT1_MASK);
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outb(1, EISA_INT2_MASK);
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outb(0xfb, EISA_INT1_MASK);
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outb(0xff, EISA_INT2_MASK);
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outb(0, EISA_DMA2_WRITE_SINGLE);
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2005-04-16 16:20:36 -06:00
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for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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if (i < (SGINT_EISA + 8))
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 03:24:36 -06:00
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irq_desc[i].chip = &ip22_eisa1_irq_type;
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2005-04-16 16:20:36 -06:00
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else
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 03:24:36 -06:00
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irq_desc[i].chip = &ip22_eisa2_irq_type;
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2005-04-16 16:20:36 -06:00
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}
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/* Cannot use request_irq because of kmalloc not being ready at such
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* an early stage. Yes, I've been bitten... */
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setup_irq(SGI_EISA_IRQ, &eisa_action);
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setup_irq(SGINT_EISA + 2, &cascade_action);
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EISA_bus = 1;
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return 0;
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}
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