2018-08-10 04:26:49 -06:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2011-10-06 12:26:35 -06:00
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/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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2016-06-15 09:05:07 -06:00
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* Copyright (C) 2011, 2015, 2016 Intel Corporation.
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2011-10-06 12:26:35 -06:00
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*/
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2016-06-15 09:05:07 -06:00
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#include <linux/acpi.h>
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2011-10-06 12:26:35 -06:00
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#include <linux/delay.h>
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#include <linux/err.h>
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2016-06-15 09:05:07 -06:00
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#include <linux/errno.h>
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#include <linux/i2c.h>
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2011-10-06 12:26:35 -06:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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2016-06-15 09:05:07 -06:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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2011-10-06 12:26:35 -06:00
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#include <linux/pci.h>
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2011-10-06 12:26:36 -06:00
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#include <linux/pm_runtime.h>
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2016-06-15 09:05:07 -06:00
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#include <linux/sched.h>
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#include <linux/slab.h>
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2011-10-06 12:26:35 -06:00
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#include "i2c-designware-core.h"
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#define DRIVER_NAME "i2c-designware-pci"
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enum dw_pci_ctl_id_t {
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2016-06-15 09:05:05 -06:00
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medfield,
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2016-06-15 09:05:06 -06:00
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merrifield,
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2014-02-19 07:10:29 -07:00
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baytrail,
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2017-02-10 03:27:58 -07:00
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cherrytrail,
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2014-05-15 08:37:24 -06:00
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haswell,
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2011-10-06 12:26:35 -06:00
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};
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2014-03-11 05:33:45 -06:00
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struct dw_scl_sda_cfg {
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 sda_hold;
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};
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2011-10-06 12:26:35 -06:00
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struct dw_pci_controller {
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u32 bus_num;
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u32 bus_cfg;
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u32 tx_fifo_depth;
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u32 rx_fifo_depth;
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u32 clk_khz;
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2014-03-07 07:12:50 -07:00
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u32 functionality;
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2017-02-10 03:27:58 -07:00
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u32 flags;
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2014-03-11 05:33:45 -06:00
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struct dw_scl_sda_cfg *scl_sda_cfg;
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2016-06-15 09:05:05 -06:00
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int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
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2011-10-06 12:26:35 -06:00
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};
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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DW_IC_CON_SLAVE_DISABLE | \
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DW_IC_CON_RESTART_EN)
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2016-06-15 09:05:06 -06:00
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/* Merrifield HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg mrfld_config = {
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.ss_hcnt = 0x2f8,
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.fs_hcnt = 0x87,
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.ss_lcnt = 0x37b,
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.fs_lcnt = 0x10a,
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};
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2014-03-11 05:33:45 -06:00
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/* BayTrail HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg byt_config = {
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.ss_hcnt = 0x200,
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.fs_hcnt = 0x55,
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.ss_lcnt = 0x200,
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.fs_lcnt = 0x99,
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.sda_hold = 0x6,
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};
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2014-05-15 08:37:24 -06:00
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/* Haswell HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg hsw_config = {
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.ss_hcnt = 0x01b0,
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.fs_hcnt = 0x48,
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.ss_lcnt = 0x01fb,
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.fs_lcnt = 0xa0,
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.sda_hold = 0x9,
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};
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2016-06-15 09:05:05 -06:00
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static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
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{
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switch (pdev->device) {
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case 0x0817:
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c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
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c->bus_cfg |= DW_IC_CON_SPEED_STD;
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2018-07-03 13:10:55 -06:00
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/* fall through */
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2016-06-15 09:05:05 -06:00
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case 0x0818:
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case 0x0819:
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c->bus_num = pdev->device - 0x817 + 3;
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return 0;
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case 0x082C:
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case 0x082D:
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case 0x082E:
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c->bus_num = pdev->device - 0x82C + 0;
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return 0;
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}
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return -ENODEV;
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}
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2016-06-15 09:05:06 -06:00
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static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
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{
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/*
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2016-06-20 02:58:09 -06:00
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* On Intel Merrifield the user visible i2c busses are enumerated
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* [1..7]. So, we add 1 to shift the default range. Besides that the
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* first PCI slot provides 4 functions, that's why we have to add 0 to
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* the first slot and 4 to the next one.
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2016-06-15 09:05:06 -06:00
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*/
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switch (PCI_SLOT(pdev->devfn)) {
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case 8:
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c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
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return 0;
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case 9:
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c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
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return 0;
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}
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return -ENODEV;
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}
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2015-02-06 04:47:02 -07:00
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static struct dw_pci_controller dw_pci_controllers[] = {
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2016-06-15 09:05:05 -06:00
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[medfield] = {
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.bus_num = -1,
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2011-10-06 12:26:35 -06:00
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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2016-11-30 09:34:15 -07:00
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.functionality = I2C_FUNC_10BIT_ADDR,
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2011-10-06 12:26:35 -06:00
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.clk_khz = 25000,
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2016-06-15 09:05:05 -06:00
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.setup = mfld_setup,
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2011-10-06 12:26:35 -06:00
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},
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2016-06-15 09:05:06 -06:00
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[merrifield] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 64,
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.rx_fifo_depth = 64,
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2016-11-30 09:34:15 -07:00
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.functionality = I2C_FUNC_10BIT_ADDR,
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2016-06-15 09:05:06 -06:00
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.scl_sda_cfg = &mrfld_config,
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.setup = mrfld_setup,
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},
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2014-02-19 07:10:29 -07:00
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[baytrail] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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2014-03-07 07:12:50 -07:00
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.functionality = I2C_FUNC_10BIT_ADDR,
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2014-03-11 05:33:45 -06:00
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.scl_sda_cfg = &byt_config,
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2014-02-19 07:10:29 -07:00
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},
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2014-05-15 08:37:24 -06:00
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[haswell] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.scl_sda_cfg = &hsw_config,
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},
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2017-02-10 03:27:58 -07:00
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[cherrytrail] = {
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.bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.functionality = I2C_FUNC_10BIT_ADDR,
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.flags = MODEL_CHERRYTRAIL,
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.scl_sda_cfg = &byt_config,
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},
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2011-10-06 12:26:35 -06:00
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};
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2014-07-23 06:06:57 -06:00
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2014-02-04 05:37:07 -07:00
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#ifdef CONFIG_PM
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2011-10-06 12:26:37 -06:00
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static int i2c_dw_pci_suspend(struct device *dev)
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2011-10-06 12:26:36 -06:00
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{
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2015-12-27 03:45:59 -07:00
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struct pci_dev *pdev = to_pci_dev(dev);
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2017-06-14 04:43:23 -06:00
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struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
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2019-02-22 06:08:40 -07:00
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i_dev->suspended = true;
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2017-06-14 04:43:23 -06:00
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i_dev->disable(i_dev);
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2011-10-06 12:26:36 -06:00
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return 0;
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}
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2011-10-06 12:26:37 -06:00
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static int i2c_dw_pci_resume(struct device *dev)
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2011-10-06 12:26:36 -06:00
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{
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2015-12-27 03:45:59 -07:00
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struct pci_dev *pdev = to_pci_dev(dev);
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2017-06-14 04:43:23 -06:00
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struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
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2019-02-22 06:08:40 -07:00
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int ret;
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2011-10-06 12:26:36 -06:00
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2019-02-22 06:08:40 -07:00
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ret = i_dev->init(i_dev);
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i_dev->suspended = false;
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return ret;
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2011-10-06 12:26:36 -06:00
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}
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2014-02-04 05:37:07 -07:00
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#endif
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2011-10-06 12:26:36 -06:00
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2014-02-04 05:37:07 -07:00
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static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
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i2c_dw_pci_resume, NULL);
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2011-10-06 12:26:36 -06:00
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2011-10-06 12:26:35 -06:00
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static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
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{
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return dev->controller->clk_khz;
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}
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2012-11-27 13:59:38 -07:00
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static int i2c_dw_pci_probe(struct pci_dev *pdev,
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2013-04-09 18:36:37 -06:00
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const struct pci_device_id *id)
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2011-10-06 12:26:35 -06:00
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{
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struct dw_i2c_dev *dev;
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struct i2c_adapter *adap;
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int r;
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2016-06-15 09:05:07 -06:00
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struct dw_pci_controller *controller;
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2014-03-11 05:33:45 -06:00
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struct dw_scl_sda_cfg *cfg;
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2011-10-06 12:26:35 -06:00
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if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
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2013-04-09 18:36:37 -06:00
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dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
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2011-10-06 12:26:35 -06:00
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id->driver_data);
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return -EINVAL;
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}
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controller = &dw_pci_controllers[id->driver_data];
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2013-04-09 18:36:38 -06:00
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r = pcim_enable_device(pdev);
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2011-10-06 12:26:35 -06:00
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if (r) {
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dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
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r);
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2013-04-09 18:36:38 -06:00
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return r;
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2011-10-06 12:26:35 -06:00
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}
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2013-04-09 18:36:38 -06:00
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r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
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2011-10-06 12:26:35 -06:00
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if (r) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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2013-04-09 18:36:38 -06:00
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return r;
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2011-10-06 12:26:35 -06:00
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}
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2013-04-09 18:36:38 -06:00
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dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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2011-10-06 12:26:35 -06:00
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dev->clk = NULL;
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dev->controller = controller;
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dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
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2013-04-09 18:36:38 -06:00
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dev->base = pcim_iomap_table(pdev)[0];
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dev->dev = &pdev->dev;
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2015-10-12 07:55:35 -06:00
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dev->irq = pdev->irq;
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2017-02-10 03:27:58 -07:00
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dev->flags |= controller->flags;
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2016-06-15 09:05:05 -06:00
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if (controller->setup) {
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r = controller->setup(pdev, controller);
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if (r)
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return r;
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}
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2014-03-07 07:12:50 -07:00
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dev->functionality = controller->functionality |
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2016-11-21 03:43:20 -07:00
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DW_IC_DEFAULT_FUNCTIONALITY;
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2014-03-07 07:12:50 -07:00
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2015-02-06 04:47:02 -07:00
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dev->master_cfg = controller->bus_cfg;
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2014-03-11 05:33:45 -06:00
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if (controller->scl_sda_cfg) {
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cfg = controller->scl_sda_cfg;
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dev->ss_hcnt = cfg->ss_hcnt;
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dev->fs_hcnt = cfg->fs_hcnt;
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dev->ss_lcnt = cfg->ss_lcnt;
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dev->fs_lcnt = cfg->fs_lcnt;
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dev->sda_hold_time = cfg->sda_hold;
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}
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2011-10-06 12:26:35 -06:00
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pci_set_drvdata(pdev, dev);
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dev->tx_fifo_depth = controller->tx_fifo_depth;
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dev->rx_fifo_depth = controller->rx_fifo_depth;
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adap = &dev->adapter;
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adap->owner = THIS_MODULE;
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adap->class = 0;
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2015-10-23 13:27:07 -06:00
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ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
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2011-10-06 12:26:35 -06:00
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adap->nr = controller->bus_num;
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2014-02-19 07:10:29 -07:00
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2015-10-12 07:55:35 -06:00
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r = i2c_dw_probe(dev);
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if (r)
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2013-04-09 18:36:38 -06:00
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return r;
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2011-10-06 12:26:35 -06:00
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2013-04-09 18:36:42 -06:00
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pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
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pm_runtime_use_autosuspend(&pdev->dev);
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2014-02-04 05:37:07 -07:00
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pm_runtime_put_autosuspend(&pdev->dev);
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2011-10-06 12:26:36 -06:00
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pm_runtime_allow(&pdev->dev);
|
|
|
|
|
2011-10-06 12:26:35 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-27 13:59:38 -07:00
|
|
|
static void i2c_dw_pci_remove(struct pci_dev *pdev)
|
2011-10-06 12:26:35 -06:00
|
|
|
{
|
|
|
|
struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
|
|
|
|
|
2017-06-14 04:43:23 -06:00
|
|
|
dev->disable(dev);
|
2011-10-06 12:26:36 -06:00
|
|
|
pm_runtime_forbid(&pdev->dev);
|
|
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
|
2011-10-06 12:26:35 -06:00
|
|
|
i2c_del_adapter(&dev->adapter);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* work with hotplug and coldplug */
|
|
|
|
MODULE_ALIAS("i2c_designware-pci");
|
|
|
|
|
2013-12-02 16:11:20 -07:00
|
|
|
static const struct pci_device_id i2_designware_pci_ids[] = {
|
2011-10-06 12:26:35 -06:00
|
|
|
/* Medfield */
|
2016-06-15 09:05:05 -06:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x0817), medfield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0818), medfield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0819), medfield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x082C), medfield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x082D), medfield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x082E), medfield },
|
2016-06-15 09:05:06 -06:00
|
|
|
/* Merrifield */
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
|
2014-02-19 07:10:29 -07:00
|
|
|
/* Baytrail */
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
|
2014-05-15 08:37:24 -06:00
|
|
|
/* Haswell */
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
|
2014-07-23 06:06:57 -06:00
|
|
|
/* Braswell / Cherrytrail */
|
2017-02-10 03:27:58 -07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
|
2011-10-06 12:26:35 -06:00
|
|
|
{ 0,}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
|
|
|
|
|
|
|
|
static struct pci_driver dw_i2c_driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.id_table = i2_designware_pci_ids,
|
|
|
|
.probe = i2c_dw_pci_probe,
|
2012-11-27 13:59:38 -07:00
|
|
|
.remove = i2c_dw_pci_remove,
|
2011-10-06 12:26:36 -06:00
|
|
|
.driver = {
|
|
|
|
.pm = &i2c_dw_pm_ops,
|
|
|
|
},
|
2011-10-06 12:26:35 -06:00
|
|
|
};
|
|
|
|
|
2012-07-24 06:13:56 -06:00
|
|
|
module_pci_driver(dw_i2c_driver);
|
2011-10-06 12:26:35 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
|
|
|
|
MODULE_LICENSE("GPL");
|