2012-10-16 01:25:43 -06:00
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/*
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* TI Touch Screen / ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/pm_runtime.h>
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2013-01-23 20:45:09 -07:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2013-12-19 08:28:31 -07:00
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#include <linux/sched.h>
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2012-10-16 01:25:43 -06:00
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#include <linux/mfd/ti_am335x_tscadc.h>
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static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
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{
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unsigned int val;
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regmap_read(tsadc->regmap_tscadc, reg, &val);
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return val;
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}
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static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
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unsigned int val)
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{
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regmap_write(tsadc->regmap_tscadc, reg, val);
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}
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static const struct regmap_config tscadc_regmap_config = {
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.name = "ti_tscadc",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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2013-12-19 08:28:29 -07:00
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
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2013-01-23 20:45:05 -07:00
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{
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2013-10-22 08:12:39 -06:00
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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2013-12-19 08:28:31 -07:00
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tsadc->reg_se_cache = val;
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if (tsadc->adc_waiting)
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wake_up(&tsadc->reg_se_wait);
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else if (!tsadc->adc_in_use)
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tscadc_writel(tsadc, REG_SE, val);
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2013-10-22 08:12:39 -06:00
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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2013-01-23 20:45:05 -07:00
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}
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2013-12-19 08:28:29 -07:00
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
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2013-12-19 08:28:31 -07:00
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static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
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{
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DEFINE_WAIT(wait);
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u32 reg;
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/*
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* disable TSC steps so it does not run while the ADC is using it. If
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* write 0 while it is running (it just started or was already running)
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* then it completes all steps that were enabled and stops then.
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*/
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tscadc_writel(tsadc, REG_SE, 0);
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reg = tscadc_readl(tsadc, REG_ADCFSM);
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if (reg & SEQ_STATUS) {
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tsadc->adc_waiting = true;
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prepare_to_wait(&tsadc->reg_se_wait, &wait,
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TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&tsadc->reg_lock);
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schedule();
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spin_lock_irq(&tsadc->reg_lock);
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finish_wait(&tsadc->reg_se_wait, &wait);
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reg = tscadc_readl(tsadc, REG_ADCFSM);
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WARN_ON(reg & SEQ_STATUS);
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tsadc->adc_waiting = false;
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}
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tsadc->adc_in_use = true;
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}
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2013-12-19 08:28:29 -07:00
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
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2013-12-19 08:28:31 -07:00
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{
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spin_lock_irq(&tsadc->reg_lock);
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am335x_tscadc_need_adc(tsadc);
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tscadc_writel(tsadc, REG_SE, val);
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spin_unlock_irq(&tsadc->reg_lock);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
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void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
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2013-12-19 08:28:29 -07:00
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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2013-12-19 08:28:31 -07:00
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tsadc->adc_in_use = false;
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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2013-12-19 08:28:29 -07:00
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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2013-12-19 08:28:31 -07:00
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EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
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2013-01-23 20:45:05 -07:00
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
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{
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2013-10-22 08:12:39 -06:00
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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2013-01-23 20:45:05 -07:00
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tsadc->reg_se_cache &= ~val;
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2013-12-19 08:28:31 -07:00
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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2013-10-22 08:12:39 -06:00
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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2013-01-23 20:45:05 -07:00
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
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2012-10-16 01:25:43 -06:00
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static void tscadc_idle_config(struct ti_tscadc_dev *config)
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{
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unsigned int idleconfig;
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idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
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STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
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tscadc_writel(config, REG_IDLECONFIG, idleconfig);
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}
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2012-12-21 16:03:15 -07:00
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static int ti_tscadc_probe(struct platform_device *pdev)
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2012-10-16 01:25:43 -06:00
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{
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struct ti_tscadc_dev *tscadc;
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struct resource *res;
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struct clk *clk;
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2013-01-23 20:45:09 -07:00
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struct device_node *node = pdev->dev.of_node;
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2012-10-16 01:25:44 -06:00
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struct mfd_cell *cell;
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2013-05-29 09:39:02 -06:00
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struct property *prop;
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const __be32 *cur;
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u32 val;
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2012-10-16 01:25:43 -06:00
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int err, ctrl;
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2013-09-23 14:43:29 -06:00
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int clock_rate;
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2013-01-23 20:45:09 -07:00
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int tsc_wires = 0, adc_channels = 0, total_channels;
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2013-05-29 09:39:02 -06:00
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int readouts = 0;
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2012-10-16 01:25:43 -06:00
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2013-05-21 09:56:49 -06:00
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "Could not find valid DT data.\n");
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2012-10-16 01:25:43 -06:00
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return -EINVAL;
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}
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2013-05-21 09:56:49 -06:00
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node = of_get_child_by_name(pdev->dev.of_node, "tsc");
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of_property_read_u32(node, "ti,wires", &tsc_wires);
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2013-05-29 09:39:02 -06:00
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of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
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2013-01-23 20:45:09 -07:00
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2013-05-21 09:56:49 -06:00
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node = of_get_child_by_name(pdev->dev.of_node, "adc");
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2013-05-29 09:39:02 -06:00
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of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
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adc_channels++;
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if (val > 7) {
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dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
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val);
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return -EINVAL;
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}
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}
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2012-10-16 01:25:45 -06:00
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total_channels = tsc_wires + adc_channels;
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if (total_channels > 8) {
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dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
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return -EINVAL;
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}
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2012-10-13 07:37:24 -06:00
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if (total_channels == 0) {
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dev_err(&pdev->dev, "Need atleast one channel.\n");
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return -EINVAL;
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}
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2012-10-16 01:25:44 -06:00
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2013-05-29 09:39:02 -06:00
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if (readouts * 2 + 2 + adc_channels > 16) {
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dev_err(&pdev->dev, "Too many step configurations requested\n");
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return -EINVAL;
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}
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2012-10-16 01:25:43 -06:00
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/* Allocate memory for device */
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tscadc = devm_kzalloc(&pdev->dev,
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sizeof(struct ti_tscadc_dev), GFP_KERNEL);
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if (!tscadc) {
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dev_err(&pdev->dev, "failed to allocate memory.\n");
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return -ENOMEM;
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}
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tscadc->dev = &pdev->dev;
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2012-11-06 01:09:03 -07:00
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err = platform_get_irq(pdev, 0);
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if (err < 0) {
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dev_err(&pdev->dev, "no irq ID is specified.\n");
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goto ret;
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} else
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tscadc->irq = err;
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2012-10-16 01:25:43 -06:00
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2014-02-11 22:31:49 -07:00
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tscadc->tscadc_base))
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return PTR_ERR(tscadc->tscadc_base);
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2012-10-16 01:25:43 -06:00
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tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
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tscadc->tscadc_base, &tscadc_regmap_config);
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if (IS_ERR(tscadc->regmap_tscadc)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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err = PTR_ERR(tscadc->regmap_tscadc);
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2012-11-06 01:09:03 -07:00
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goto ret;
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2012-10-16 01:25:43 -06:00
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}
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2013-01-23 20:45:05 -07:00
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spin_lock_init(&tscadc->reg_lock);
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2013-12-19 08:28:31 -07:00
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init_waitqueue_head(&tscadc->reg_se_wait);
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2012-10-16 01:25:43 -06:00
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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/*
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* The TSC_ADC_Subsystem has 2 clock domains
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* OCP_CLK and ADC_CLK.
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* The ADC clock is expected to run at target of 3MHz,
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* and expected to capture 12-bit data at a rate of 200 KSPS.
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* The TSC_ADC_SS controller design assumes the OCP clock is
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* at least 6x faster than the ADC clock.
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*/
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clk = clk_get(&pdev->dev, "adc_tsc_fck");
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get TSC fck\n");
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err = PTR_ERR(clk);
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goto err_disable_clk;
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}
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clock_rate = clk_get_rate(clk);
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clk_put(clk);
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2013-09-23 14:43:29 -06:00
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tscadc->clk_div = clock_rate / ADC_CLK;
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2013-07-20 10:27:35 -06:00
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2012-10-16 01:25:43 -06:00
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/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
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2013-09-23 14:43:29 -06:00
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tscadc->clk_div--;
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tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
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2012-10-16 01:25:43 -06:00
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/* Set the control register bits */
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ctrl = CNTRLREG_STEPCONFIGWRT |
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2013-07-20 10:27:34 -06:00
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CNTRLREG_STEPID;
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if (tsc_wires > 0)
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ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
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2012-10-16 01:25:43 -06:00
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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/* Set register bits for Idle Config Mode */
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2013-07-20 10:27:34 -06:00
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if (tsc_wires > 0)
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tscadc_idle_config(tscadc);
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2012-10-16 01:25:43 -06:00
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/* Enable the TSC module enable bit */
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ctrl = tscadc_readl(tscadc, REG_CTRL);
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ctrl |= CNTRLREG_TSCSSENB;
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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2012-10-13 07:37:24 -06:00
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tscadc->used_cells = 0;
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tscadc->tsc_cell = -1;
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tscadc->adc_cell = -1;
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2012-10-16 01:25:44 -06:00
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/* TSC Cell */
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2012-10-13 07:37:24 -06:00
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if (tsc_wires > 0) {
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tscadc->tsc_cell = tscadc->used_cells;
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cell = &tscadc->cells[tscadc->used_cells++];
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2013-05-27 09:08:28 -06:00
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cell->name = "TI-am335x-tsc";
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2012-10-13 07:37:24 -06:00
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cell->of_compatible = "ti,am3359-tsc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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}
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2012-10-16 01:25:44 -06:00
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2012-10-16 01:25:45 -06:00
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/* ADC Cell */
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2012-10-13 07:37:24 -06:00
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if (adc_channels > 0) {
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tscadc->adc_cell = tscadc->used_cells;
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cell = &tscadc->cells[tscadc->used_cells++];
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2013-05-27 09:12:52 -06:00
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cell->name = "TI-am335x-adc";
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2012-10-13 07:37:24 -06:00
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cell->of_compatible = "ti,am3359-adc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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}
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2012-10-16 01:25:45 -06:00
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2012-10-16 01:25:43 -06:00
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err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
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2012-10-13 07:37:24 -06:00
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tscadc->used_cells, NULL, 0, NULL);
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2012-10-16 01:25:43 -06:00
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if (err < 0)
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goto err_disable_clk;
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device_init_wakeup(&pdev->dev, true);
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platform_set_drvdata(pdev, tscadc);
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return 0;
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err_disable_clk:
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pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2012-11-06 01:09:03 -07:00
|
|
|
ret:
|
2012-10-16 01:25:43 -06:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2012-12-21 16:03:15 -07:00
|
|
|
static int ti_tscadc_remove(struct platform_device *pdev)
|
2012-10-16 01:25:43 -06:00
|
|
|
{
|
|
|
|
struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
tscadc_writel(tscadc, REG_SE, 0x00);
|
|
|
|
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
|
|
|
mfd_remove_devices(tscadc->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int tscadc_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
tscadc_writel(tscadc_dev, REG_SE, 0x00);
|
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tscadc_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
|
|
|
|
unsigned int restore, ctrl;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
|
|
|
|
/* context restore */
|
2013-07-20 10:27:34 -06:00
|
|
|
ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
|
|
|
|
if (tscadc_dev->tsc_cell != -1)
|
|
|
|
ctrl |= CNTRLREG_TSCENB | CNTRLREG_4WIRE;
|
2012-10-16 01:25:43 -06:00
|
|
|
tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
|
2013-07-20 10:27:34 -06:00
|
|
|
|
|
|
|
if (tscadc_dev->tsc_cell != -1)
|
|
|
|
tscadc_idle_config(tscadc_dev);
|
2012-10-16 01:25:43 -06:00
|
|
|
restore = tscadc_readl(tscadc_dev, REG_CTRL);
|
|
|
|
tscadc_writel(tscadc_dev, REG_CTRL,
|
|
|
|
(restore | CNTRLREG_TSCSSENB));
|
|
|
|
|
2013-09-23 14:43:29 -06:00
|
|
|
tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
|
|
|
|
|
2012-10-16 01:25:43 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops tscadc_pm_ops = {
|
|
|
|
.suspend = tscadc_suspend,
|
|
|
|
.resume = tscadc_resume,
|
|
|
|
};
|
|
|
|
#define TSCADC_PM_OPS (&tscadc_pm_ops)
|
|
|
|
#else
|
|
|
|
#define TSCADC_PM_OPS NULL
|
|
|
|
#endif
|
|
|
|
|
2013-01-23 20:45:09 -07:00
|
|
|
static const struct of_device_id ti_tscadc_dt_ids[] = {
|
|
|
|
{ .compatible = "ti,am3359-tscadc", },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
|
|
|
|
|
2012-10-16 01:25:43 -06:00
|
|
|
static struct platform_driver ti_tscadc_driver = {
|
|
|
|
.driver = {
|
2013-01-23 20:45:09 -07:00
|
|
|
.name = "ti_am3359-tscadc",
|
2012-10-16 01:25:43 -06:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.pm = TSCADC_PM_OPS,
|
2013-10-14 21:48:49 -06:00
|
|
|
.of_match_table = ti_tscadc_dt_ids,
|
2012-10-16 01:25:43 -06:00
|
|
|
},
|
|
|
|
.probe = ti_tscadc_probe,
|
2012-12-21 16:03:15 -07:00
|
|
|
.remove = ti_tscadc_remove,
|
2012-10-16 01:25:43 -06:00
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(ti_tscadc_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
|
|
|
|
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|