2005-04-16 16:20:36 -06:00
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/*
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* linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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2006-06-28 07:10:01 -06:00
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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2005-04-16 16:20:36 -06:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm1020.
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*
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* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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2005-09-09 13:08:59 -06:00
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#include <asm/asm-offsets.h>
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2008-09-07 12:15:31 -06:00
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#include <asm/hwcap.h>
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2006-03-16 07:44:36 -07:00
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#include <asm/pgtable-hwdef.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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2006-07-03 05:36:07 -06:00
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#include "proc-macros.S"
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2005-04-16 16:20:36 -06:00
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* The number of data cache segments.
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*/
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#define CACHE_DSEGMENTS 16
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/*
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* The number of lines in a cache segment.
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*/
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#define CACHE_DENTRIES 64
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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2011-03-30 19:57:33 -06:00
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* cache line maintenance instructions.
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2005-04-16 16:20:36 -06:00
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*/
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#define CACHE_DLIMIT 32768
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.text
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/*
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* cpu_arm1020_proc_init()
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*/
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ENTRY(cpu_arm1020_proc_init)
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* cpu_arm1020_proc_fin()
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*/
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ENTRY(cpu_arm1020_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* cpu_arm1020_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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2011-11-15 06:25:04 -07:00
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.pushsection .idmap.text, "ax"
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2005-04-16 16:20:36 -06:00
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ENTRY(cpu_arm1020_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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2006-06-28 07:10:01 -06:00
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#ifdef CONFIG_MMU
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2005-04-16 16:20:36 -06:00
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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2006-06-28 07:10:01 -06:00
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#endif
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2005-04-16 16:20:36 -06:00
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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2014-06-30 09:29:12 -06:00
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ret r0
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2011-11-15 06:25:04 -07:00
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ENDPROC(cpu_arm1020_reset)
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.popsection
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2005-04-16 16:20:36 -06:00
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/*
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* cpu_arm1020_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm1020_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/* ================================= CACHE ================================ */
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.align 5
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2010-10-28 04:27:40 -06:00
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(arm1020_flush_icache_all)
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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#endif
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2014-06-30 09:29:12 -06:00
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ret lr
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2010-10-28 04:27:40 -06:00
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ENDPROC(arm1020_flush_icache_all)
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2005-04-16 16:20:36 -06:00
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(arm1020_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm1020_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 5
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bcs 1b @ segments 15 to 0
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags for this space
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*/
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ENTRY(arm1020_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bhs __flush_whole_cache
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, ip, c7, c10, 4
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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tst r2, #VM_EXEC
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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#endif
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1020_coherent_kern_range)
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/* FALLTRHOUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm1020_coherent_user_range)
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mov ip, #0
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcr p15, 0, ip, c7, c10, 4
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1:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#endif
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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2012-04-27 06:08:53 -06:00
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mov r0, #0
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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2009-11-26 05:56:21 -07:00
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* flush_kern_dcache_area(void *addr, size_t size)
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2005-04-16 16:20:36 -06:00
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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2009-11-26 05:56:21 -07:00
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* - addr - kernel address
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* - size - region size
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2005-04-16 16:20:36 -06:00
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*/
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2009-11-26 05:56:21 -07:00
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ENTRY(arm1020_flush_kern_dcache_area)
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2005-04-16 16:20:36 -06:00
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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2009-11-26 05:56:21 -07:00
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add r1, r0, r1
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2005-04-16 16:20:36 -06:00
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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2009-11-26 09:24:19 -07:00
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arm1020_dma_inv_range:
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2005-04-16 16:20:36 -06:00
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, ip, c7, c10, 4
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, ip, c7, c10, 4
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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2009-11-26 09:24:19 -07:00
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arm1020_dma_clean_range:
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2005-04-16 16:20:36 -06:00
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 09:29:12 -06:00
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ret lr
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2005-04-16 16:20:36 -06:00
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
|
|
|
|
*
|
|
|
|
* - start - virtual start address
|
|
|
|
* - end - virtual end address
|
|
|
|
*/
|
|
|
|
ENTRY(arm1020_dma_flush_range)
|
|
|
|
mov ip, #0
|
|
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
|
|
bic r0, r0, #CACHE_DLINESIZE - 1
|
|
|
|
mcr p15, 0, ip, c7, c10, 4
|
|
|
|
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
|
|
|
add r0, r0, #CACHE_DLINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
|
|
|
#endif
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-11-26 09:19:58 -07:00
|
|
|
/*
|
|
|
|
* dma_map_area(start, size, dir)
|
|
|
|
* - start - kernel virtual start address
|
|
|
|
* - size - size of region
|
|
|
|
* - dir - DMA direction
|
|
|
|
*/
|
|
|
|
ENTRY(arm1020_dma_map_area)
|
|
|
|
add r1, r1, r0
|
|
|
|
cmp r2, #DMA_TO_DEVICE
|
|
|
|
beq arm1020_dma_clean_range
|
|
|
|
bcs arm1020_dma_inv_range
|
|
|
|
b arm1020_dma_flush_range
|
|
|
|
ENDPROC(arm1020_dma_map_area)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* dma_unmap_area(start, size, dir)
|
|
|
|
* - start - kernel virtual start address
|
|
|
|
* - size - size of region
|
|
|
|
* - dir - DMA direction
|
|
|
|
*/
|
|
|
|
ENTRY(arm1020_dma_unmap_area)
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2009-11-26 09:19:58 -07:00
|
|
|
ENDPROC(arm1020_dma_unmap_area)
|
|
|
|
|
2012-09-06 07:05:13 -06:00
|
|
|
.globl arm1020_flush_kern_cache_louis
|
|
|
|
.equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
|
|
|
|
|
2011-06-23 10:16:44 -06:00
|
|
|
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
|
|
|
|
define_cache_functions arm1020
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
.align 5
|
|
|
|
ENTRY(cpu_arm1020_dcache_clean_area)
|
|
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
|
|
mov ip, #0
|
|
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
|
|
|
add r0, r0, #CACHE_DLINESIZE
|
|
|
|
subs r1, r1, #CACHE_DLINESIZE
|
|
|
|
bhi 1b
|
|
|
|
#endif
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* =============================== PageTable ============================== */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_arm1020_switch_mm(pgd)
|
|
|
|
*
|
|
|
|
* Set the translation base pointer to be as described by pgd.
|
|
|
|
*
|
|
|
|
* pgd: new page tables
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
ENTRY(cpu_arm1020_switch_mm)
|
2006-06-28 07:10:01 -06:00
|
|
|
#ifdef CONFIG_MMU
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
|
|
mcr p15, 0, r3, c7, c10, 4
|
|
|
|
mov r1, #0xF @ 16 segments
|
|
|
|
1: mov r3, #0x3F @ 64 entries
|
|
|
|
2: mov ip, r3, LSL #26 @ shift up entry
|
|
|
|
orr ip, ip, r1, LSL #5 @ shift in/up index
|
|
|
|
mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
|
|
|
|
mov ip, #0
|
|
|
|
mcr p15, 0, ip, c7, c10, 4
|
|
|
|
subs r3, r3, #1
|
|
|
|
cmp r3, #0
|
|
|
|
bge 2b @ entries 3F to 0
|
|
|
|
subs r1, r1, #1
|
|
|
|
cmp r1, #0
|
|
|
|
bge 1b @ segments 15 to 0
|
|
|
|
|
|
|
|
#endif
|
|
|
|
mov r1, #0
|
|
|
|
#ifndef CONFIG_CPU_ICACHE_DISABLE
|
|
|
|
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
|
|
|
|
#endif
|
|
|
|
mcr p15, 0, r1, c7, c10, 4 @ drain WB
|
|
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
|
|
|
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
|
2006-06-28 07:10:01 -06:00
|
|
|
#endif /* CONFIG_MMU */
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_arm1020_set_pte(ptep, pte)
|
|
|
|
*
|
|
|
|
* Set a PTE and flush it out
|
|
|
|
*/
|
|
|
|
.align 5
|
2006-12-13 07:34:43 -07:00
|
|
|
ENTRY(cpu_arm1020_set_pte_ext)
|
2006-06-28 07:10:01 -06:00
|
|
|
#ifdef CONFIG_MMU
|
2008-09-06 10:19:08 -06:00
|
|
|
armv3_set_pte_ext
|
2005-04-16 16:20:36 -06:00
|
|
|
mov r0, r0
|
|
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
|
|
mcr p15, 0, r0, c7, c10, 4
|
|
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
|
|
#endif
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
2006-06-28 07:10:01 -06:00
|
|
|
#endif /* CONFIG_MMU */
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
.type __arm1020_setup, #function
|
|
|
|
__arm1020_setup:
|
|
|
|
mov r0, #0
|
|
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
2006-06-28 07:10:01 -06:00
|
|
|
#ifdef CONFIG_MMU
|
2005-04-16 16:20:36 -06:00
|
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
2006-06-28 07:10:01 -06:00
|
|
|
#endif
|
2006-06-29 08:09:57 -06:00
|
|
|
|
|
|
|
adr r5, arm1020_crval
|
|
|
|
ldmia r5, {r5, r6}
|
2005-04-16 16:20:36 -06:00
|
|
|
mrc p15, 0, r0, c1, c0 @ get control register v4
|
|
|
|
bic r0, r0, r5
|
2006-06-29 08:09:57 -06:00
|
|
|
orr r0, r0, r6
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
|
|
|
orr r0, r0, #0x4000 @ .R.. .... .... ....
|
|
|
|
#endif
|
2014-06-30 09:29:12 -06:00
|
|
|
ret lr
|
2005-04-16 16:20:36 -06:00
|
|
|
.size __arm1020_setup, . - __arm1020_setup
|
|
|
|
|
|
|
|
/*
|
|
|
|
* R
|
|
|
|
* .RVI ZFRS BLDP WCAM
|
2005-06-30 10:04:14 -06:00
|
|
|
* .011 1001 ..11 0101
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
2006-06-29 08:09:57 -06:00
|
|
|
.type arm1020_crval, #object
|
|
|
|
arm1020_crval:
|
|
|
|
crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
__INITDATA
|
2011-06-23 10:16:44 -06:00
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
|
|
define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
|
|
|
|
.section ".rodata"
|
|
|
|
|
2011-06-23 10:16:44 -06:00
|
|
|
string cpu_arch_name, "armv5t"
|
|
|
|
string cpu_elf_name, "v5"
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
.type cpu_arm1020_name, #object
|
|
|
|
cpu_arm1020_name:
|
|
|
|
.ascii "ARM1020"
|
|
|
|
#ifndef CONFIG_CPU_ICACHE_DISABLE
|
|
|
|
.ascii "i"
|
|
|
|
#endif
|
|
|
|
#ifndef CONFIG_CPU_DCACHE_DISABLE
|
|
|
|
.ascii "d"
|
|
|
|
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
|
|
|
.ascii "(wt)"
|
|
|
|
#else
|
|
|
|
.ascii "(wb)"
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#ifndef CONFIG_CPU_BPREDICT_DISABLE
|
|
|
|
.ascii "B"
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
|
|
|
.ascii "RR"
|
|
|
|
#endif
|
|
|
|
.ascii "\0"
|
|
|
|
.size cpu_arm1020_name, . - cpu_arm1020_name
|
|
|
|
|
|
|
|
.align
|
|
|
|
|
2005-09-20 09:35:03 -06:00
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
.type __arm1020_proc_info,#object
|
|
|
|
__arm1020_proc_info:
|
|
|
|
.long 0x4104a200 @ ARM 1020T (Architecture v5T)
|
|
|
|
.long 0xff0ffff0
|
2006-06-29 11:24:21 -06:00
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
2005-04-16 16:20:36 -06:00
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
|
|
|
b __arm1020_setup
|
|
|
|
.long cpu_arch_name
|
|
|
|
.long cpu_elf_name
|
|
|
|
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
|
|
|
|
.long cpu_arm1020_name
|
|
|
|
.long arm1020_processor_functions
|
|
|
|
.long v4wbi_tlb_fns
|
|
|
|
.long v4wb_user_fns
|
|
|
|
.long arm1020_cache_fns
|
|
|
|
.size __arm1020_proc_info, . - __arm1020_proc_info
|