2006-01-02 02:14:23 -07:00
|
|
|
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
2006-01-02 02:14:23 -07:00
|
|
|
/*
|
2005-04-16 16:20:36 -06:00
|
|
|
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
|
2005-06-23 06:46:46 -06:00
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|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
|
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|
|
* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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|
* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
|
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
|
2006-01-02 02:14:23 -07:00
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*/
|
2005-04-16 16:20:36 -06:00
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2009-06-18 17:56:52 -06:00
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#include <linux/sysrq.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
|
|
|
#include <linux/slab.h>
|
2005-04-16 16:20:36 -06:00
|
|
|
#include "drmP.h"
|
|
|
|
#include "drm.h"
|
|
|
|
#include "i915_drm.h"
|
|
|
|
#include "i915_drv.h"
|
2009-08-25 04:15:50 -06:00
|
|
|
#include "i915_trace.h"
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
#include "intel_drv.h"
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
#define MAX_NOPID ((u32)~0)
|
|
|
|
|
2008-11-04 03:03:27 -07:00
|
|
|
/**
|
|
|
|
* Interrupts that are always left unmasked.
|
|
|
|
*
|
|
|
|
* Since pipe events are edge-triggered from the PIPESTAT register to IIR,
|
|
|
|
* we leave them always unmasked in IMR and then control enabling them through
|
|
|
|
* PIPESTAT alone.
|
|
|
|
*/
|
2009-11-18 09:25:18 -07:00
|
|
|
#define I915_INTERRUPT_ENABLE_FIX \
|
|
|
|
(I915_ASLE_INTERRUPT | \
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2008-11-04 03:03:27 -07:00
|
|
|
|
|
|
|
/** Interrupts that we mask and unmask at runtime. */
|
2010-05-20 19:08:57 -06:00
|
|
|
#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
|
2008-11-04 03:03:27 -07:00
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
|
|
|
|
PIPE_VBLANK_INTERRUPT_STATUS)
|
|
|
|
|
|
|
|
#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
|
|
|
|
PIPE_VBLANK_INTERRUPT_ENABLE)
|
|
|
|
|
|
|
|
#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
|
|
|
|
DRM_I915_VBLANK_PIPE_B)
|
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
/* For display hotplug interrupt */
|
2010-08-20 06:23:26 -06:00
|
|
|
static void
|
2009-12-03 15:14:42 -07:00
|
|
|
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
2010-12-04 04:30:53 -07:00
|
|
|
if ((dev_priv->irq_mask & mask) != 0) {
|
|
|
|
dev_priv->irq_mask &= ~mask;
|
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 00:40:19 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
2009-12-03 15:14:42 -07:00
|
|
|
ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
2010-12-04 04:30:53 -07:00
|
|
|
if ((dev_priv->irq_mask & mask) != mask) {
|
|
|
|
dev_priv->irq_mask |= mask;
|
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 00:40:19 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-04 03:03:27 -07:00
|
|
|
void
|
|
|
|
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
|
|
|
|
{
|
|
|
|
if ((dev_priv->pipestat[pipe] & mask) != mask) {
|
2011-02-07 13:26:52 -07:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2008-11-04 03:03:27 -07:00
|
|
|
|
|
|
|
dev_priv->pipestat[pipe] |= mask;
|
|
|
|
/* Enable the interrupt, clear any pending status */
|
|
|
|
I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(reg);
|
2008-11-04 03:03:27 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
|
|
|
|
{
|
|
|
|
if ((dev_priv->pipestat[pipe] & mask) != 0) {
|
2011-02-07 13:26:52 -07:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2008-11-04 03:03:27 -07:00
|
|
|
|
|
|
|
dev_priv->pipestat[pipe] &= ~mask;
|
|
|
|
I915_WRITE(reg, dev_priv->pipestat[pipe]);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(reg);
|
2008-11-04 03:03:27 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-27 23:10:00 -06:00
|
|
|
/**
|
|
|
|
* intel_enable_asle - enable ASLE interrupt for OpRegion
|
|
|
|
*/
|
2010-12-04 04:30:53 -07:00
|
|
|
void intel_enable_asle(struct drm_device *dev)
|
2009-10-27 23:10:00 -06:00
|
|
|
{
|
2010-12-04 04:30:53 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2009-10-27 23:10:00 -06:00
|
|
|
|
2010-01-28 17:45:52 -07:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
2009-12-03 15:14:42 -07:00
|
|
|
ironlake_enable_display_irq(dev_priv, DE_GSE);
|
2010-04-07 03:11:21 -06:00
|
|
|
else {
|
2009-10-27 23:10:00 -06:00
|
|
|
i915_enable_pipestat(dev_priv, 1,
|
2010-06-30 14:16:00 -06:00
|
|
|
PIPE_LEGACY_BLC_EVENT_ENABLE);
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2010-04-07 03:11:21 -06:00
|
|
|
i915_enable_pipestat(dev_priv, 0,
|
2010-06-30 14:16:00 -06:00
|
|
|
PIPE_LEGACY_BLC_EVENT_ENABLE);
|
2010-04-07 03:11:21 -06:00
|
|
|
}
|
2010-12-04 04:30:53 -07:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2009-10-27 23:10:00 -06:00
|
|
|
}
|
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
/**
|
|
|
|
* i915_pipe_enabled - check if a pipe is enabled
|
|
|
|
* @dev: DRM device
|
|
|
|
* @pipe: pipe to check
|
|
|
|
*
|
|
|
|
* Reading certain registers when the pipe is disabled can hang the chip.
|
|
|
|
* Use this routine to make sure the PLL is running and the pipe is active
|
|
|
|
* before reading such registers if unsure.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
i915_pipe_enabled(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2010-09-11 06:48:45 -06:00
|
|
|
return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
|
2008-09-30 13:14:26 -06:00
|
|
|
}
|
|
|
|
|
2008-10-18 20:39:29 -06:00
|
|
|
/* Called from drm generic code, passed a 'crtc', which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 14:00:41 -06:00
|
|
|
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
|
2008-09-30 13:14:26 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long high_frame;
|
|
|
|
unsigned long low_frame;
|
2010-09-11 06:48:45 -06:00
|
|
|
u32 high1, high2, low;
|
2008-09-30 13:14:26 -06:00
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe)) {
|
2009-10-08 21:39:40 -06:00
|
|
|
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
|
2011-02-07 13:26:52 -07:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2008-09-30 13:14:26 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
high_frame = PIPEFRAME(pipe);
|
|
|
|
low_frame = PIPEFRAMEPIXEL(pipe);
|
2010-09-11 06:48:45 -06:00
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
/*
|
|
|
|
* High & low register fields aren't synchronized, so make sure
|
|
|
|
* we get a low value that's stable across two reads of the high
|
|
|
|
* register.
|
|
|
|
*/
|
|
|
|
do {
|
2010-09-11 06:48:45 -06:00
|
|
|
high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
|
|
|
low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
|
|
|
|
high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
2008-09-30 13:14:26 -06:00
|
|
|
} while (high1 != high2);
|
|
|
|
|
2010-09-11 06:48:45 -06:00
|
|
|
high1 >>= PIPE_FRAME_HIGH_SHIFT;
|
|
|
|
low >>= PIPE_FRAME_LOW_SHIFT;
|
|
|
|
return (high1 << 8) | low;
|
2008-09-30 13:14:26 -06:00
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
|
2009-02-06 11:22:41 -07:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2011-02-07 13:26:52 -07:00
|
|
|
int reg = PIPE_FRMCOUNT_GM45(pipe);
|
2009-02-06 11:22:41 -07:00
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe)) {
|
2009-10-08 21:39:40 -06:00
|
|
|
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
|
2011-02-07 13:26:52 -07:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2009-02-06 11:22:41 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return I915_READ(reg);
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
|
2010-12-07 20:07:19 -07:00
|
|
|
int *vpos, int *hpos)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
u32 vbl = 0, position = 0;
|
|
|
|
int vbl_start, vbl_end, htotal, vtotal;
|
|
|
|
bool in_vbl = true;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe)) {
|
|
|
|
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
|
2011-02-07 13:26:52 -07:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2010-12-07 20:07:19 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get vtotal. */
|
|
|
|
vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
|
|
/* No obvious pixelcount register. Only query vertical
|
|
|
|
* scanout position from Display scan line register.
|
|
|
|
*/
|
|
|
|
position = I915_READ(PIPEDSL(pipe));
|
|
|
|
|
|
|
|
/* Decode into vertical scanout position. Don't have
|
|
|
|
* horizontal scanout position.
|
|
|
|
*/
|
|
|
|
*vpos = position & 0x1fff;
|
|
|
|
*hpos = 0;
|
|
|
|
} else {
|
|
|
|
/* Have access to pixelcount since start of frame.
|
|
|
|
* We can split this into vertical and horizontal
|
|
|
|
* scanout position.
|
|
|
|
*/
|
|
|
|
position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
|
|
|
|
|
|
|
|
htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
|
|
|
|
*vpos = position / htotal;
|
|
|
|
*hpos = position - (*vpos * htotal);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Query vblank area. */
|
|
|
|
vbl = I915_READ(VBLANK(pipe));
|
|
|
|
|
|
|
|
/* Test position against vblank region. */
|
|
|
|
vbl_start = vbl & 0x1fff;
|
|
|
|
vbl_end = (vbl >> 16) & 0x1fff;
|
|
|
|
|
|
|
|
if ((*vpos < vbl_start) || (*vpos > vbl_end))
|
|
|
|
in_vbl = false;
|
|
|
|
|
|
|
|
/* Inside "upper part" of vblank area? Apply corrective offset: */
|
|
|
|
if (in_vbl && (*vpos >= vbl_start))
|
|
|
|
*vpos = *vpos - vtotal;
|
|
|
|
|
|
|
|
/* Readouts valid? */
|
|
|
|
if (vbl > 0)
|
|
|
|
ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
|
|
|
|
|
|
|
|
/* In vblank? */
|
|
|
|
if (in_vbl)
|
|
|
|
ret |= DRM_SCANOUTPOS_INVBL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
|
2010-12-07 20:07:19 -07:00
|
|
|
int *max_error,
|
|
|
|
struct timeval *vblank_time,
|
|
|
|
unsigned flags)
|
|
|
|
{
|
2011-01-22 03:07:56 -07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc;
|
2010-12-07 20:07:19 -07:00
|
|
|
|
2011-01-22 03:07:56 -07:00
|
|
|
if (pipe < 0 || pipe >= dev_priv->num_pipe) {
|
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
2010-12-07 20:07:19 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get drm_crtc to timestamp: */
|
2011-01-22 03:07:56 -07:00
|
|
|
crtc = intel_get_crtc_for_pipe(dev, pipe);
|
|
|
|
if (crtc == NULL) {
|
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!crtc->enabled) {
|
|
|
|
DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2010-12-07 20:07:19 -07:00
|
|
|
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
2011-01-22 03:07:56 -07:00
|
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
|
|
|
|
vblank_time, flags,
|
|
|
|
crtc);
|
2010-12-07 20:07:19 -07:00
|
|
|
}
|
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
/*
|
|
|
|
* Handle hotplug events outside the interrupt handler proper.
|
|
|
|
*/
|
|
|
|
static void i915_hotplug_work_func(struct work_struct *work)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
|
|
|
|
hotplug_work);
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2009-05-06 12:48:58 -06:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
2010-09-09 08:14:28 -06:00
|
|
|
struct intel_encoder *encoder;
|
|
|
|
|
2011-07-25 11:04:56 -06:00
|
|
|
mutex_lock(&mode_config->mutex);
|
2011-02-11 15:44:51 -07:00
|
|
|
DRM_DEBUG_KMS("running encoder hotplug functions\n");
|
|
|
|
|
2010-09-09 08:14:28 -06:00
|
|
|
list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
|
|
|
|
if (encoder->hot_plug)
|
|
|
|
encoder->hot_plug(encoder);
|
|
|
|
|
2011-07-28 16:31:19 -06:00
|
|
|
mutex_unlock(&mode_config->mutex);
|
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
/* Just fire off a uevent and let userspace tell us what to do */
|
2010-05-07 00:42:51 -06:00
|
|
|
drm_helper_hpd_irq_event(dev);
|
2009-03-31 15:11:15 -06:00
|
|
|
}
|
|
|
|
|
2010-01-29 12:27:07 -07:00
|
|
|
static void i915_handle_rps_change(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-02-02 11:30:47 -07:00
|
|
|
u32 busy_up, busy_down, max_avg, min_avg;
|
2010-01-29 12:27:07 -07:00
|
|
|
u8 new_delay = dev_priv->cur_delay;
|
|
|
|
|
2010-05-20 15:28:11 -06:00
|
|
|
I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
|
2010-02-02 11:30:47 -07:00
|
|
|
busy_up = I915_READ(RCPREVBSYTUPAVG);
|
|
|
|
busy_down = I915_READ(RCPREVBSYTDNAVG);
|
2010-01-29 12:27:07 -07:00
|
|
|
max_avg = I915_READ(RCBMAXAVG);
|
|
|
|
min_avg = I915_READ(RCBMINAVG);
|
|
|
|
|
|
|
|
/* Handle RCS change request from hw */
|
2010-02-02 11:30:47 -07:00
|
|
|
if (busy_up > max_avg) {
|
2010-01-29 12:27:07 -07:00
|
|
|
if (dev_priv->cur_delay != dev_priv->max_delay)
|
|
|
|
new_delay = dev_priv->cur_delay - 1;
|
|
|
|
if (new_delay < dev_priv->max_delay)
|
|
|
|
new_delay = dev_priv->max_delay;
|
2010-02-02 11:30:47 -07:00
|
|
|
} else if (busy_down < min_avg) {
|
2010-01-29 12:27:07 -07:00
|
|
|
if (dev_priv->cur_delay != dev_priv->min_delay)
|
|
|
|
new_delay = dev_priv->cur_delay + 1;
|
|
|
|
if (new_delay > dev_priv->min_delay)
|
|
|
|
new_delay = dev_priv->min_delay;
|
|
|
|
}
|
|
|
|
|
2010-05-20 15:28:11 -06:00
|
|
|
if (ironlake_set_drps(dev, new_delay))
|
|
|
|
dev_priv->cur_delay = new_delay;
|
2010-01-29 12:27:07 -07:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-10-19 04:19:32 -06:00
|
|
|
static void notify_ring(struct drm_device *dev,
|
|
|
|
struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-01-20 02:52:56 -07:00
|
|
|
u32 seqno;
|
2011-01-04 15:22:17 -07:00
|
|
|
|
2011-01-20 02:52:56 -07:00
|
|
|
if (ring->obj == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
seqno = ring->get_seqno(ring);
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_request_complete(ring, seqno);
|
2011-01-04 15:22:17 -07:00
|
|
|
|
|
|
|
ring->irq_seqno = seqno;
|
2010-10-19 04:19:32 -06:00
|
|
|
wake_up_all(&ring->irq_queue);
|
2011-06-29 11:26:42 -06:00
|
|
|
if (i915_enable_hangcheck) {
|
|
|
|
dev_priv->hangcheck_count = 0;
|
|
|
|
mod_timer(&dev_priv->hangcheck_timer,
|
|
|
|
jiffies +
|
|
|
|
msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
|
|
|
|
}
|
2010-10-19 04:19:32 -06:00
|
|
|
}
|
|
|
|
|
2011-04-25 12:25:20 -06:00
|
|
|
static void gen6_pm_rps_work(struct work_struct *work)
|
2010-12-17 15:19:02 -07:00
|
|
|
{
|
2011-04-25 12:25:20 -06:00
|
|
|
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
|
|
|
|
rps_work);
|
2010-12-17 15:19:02 -07:00
|
|
|
u8 new_delay = dev_priv->cur_delay;
|
2011-04-25 12:25:20 -06:00
|
|
|
u32 pm_iir, pm_imr;
|
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->rps_lock);
|
|
|
|
pm_iir = dev_priv->pm_iir;
|
|
|
|
dev_priv->pm_iir = 0;
|
|
|
|
pm_imr = I915_READ(GEN6_PMIMR);
|
drm/i915: close PM interrupt masking races in the rps work func
This patch closes the following race:
We get a PM interrupt A, mask it, set dev_priv->iir = PM_A and kick of the
work item. Scheduler isn't grumpy, so the work queue takes rps_lock,
grabs pm_iir = dev_priv->pm_iir and pm_imr = READ(PMIMR). Note that
pm_imr == pm_iir because we've just masked the interrupt we've got.
Now hw sends out PM interrupt B (not masked), we process it and mask
it. Later on the irq handler also clears PMIIR.
Then the work item proceeds and at the end clears PMIMR. Because
(local) pm_imr == pm_iir we have
pm_imr & ~pm_iir == 0
so all interrupts are enabled.
Hardware is still interrupt-happy, and sends out a new PM interrupt B.
PMIMR doesn't mask B (it does not mask anything), PMIIR is cleared, so
we get it and hit the WARN in the interrupt handler (because
dev_priv->pm_iir == PM_B).
That's why I've moved the
WRITE(PMIMR, 0)
up under the protection of the rps_lock. And write an uncoditional 0
to PMIMR, because that's what we'll do anyway.
This races looks much more likely because we can arbitrarily extend
the window by grabing dev->struct mutex right after the irq handler
has processed the first PM_B interrupt.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-08 06:00:21 -06:00
|
|
|
I915_WRITE(GEN6_PMIMR, 0);
|
2011-04-25 12:25:20 -06:00
|
|
|
spin_unlock_irq(&dev_priv->rps_lock);
|
2010-12-17 15:19:02 -07:00
|
|
|
|
|
|
|
if (!pm_iir)
|
|
|
|
return;
|
|
|
|
|
2011-04-25 12:25:20 -06:00
|
|
|
mutex_lock(&dev_priv->dev->struct_mutex);
|
2010-12-17 15:19:02 -07:00
|
|
|
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
|
|
|
|
if (dev_priv->cur_delay != dev_priv->max_delay)
|
|
|
|
new_delay = dev_priv->cur_delay + 1;
|
|
|
|
if (new_delay > dev_priv->max_delay)
|
|
|
|
new_delay = dev_priv->max_delay;
|
|
|
|
} else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
|
2011-04-25 12:25:20 -06:00
|
|
|
gen6_gt_force_wake_get(dev_priv);
|
2010-12-17 15:19:02 -07:00
|
|
|
if (dev_priv->cur_delay != dev_priv->min_delay)
|
|
|
|
new_delay = dev_priv->cur_delay - 1;
|
|
|
|
if (new_delay < dev_priv->min_delay) {
|
|
|
|
new_delay = dev_priv->min_delay;
|
|
|
|
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
|
|
|
|
I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
|
|
|
|
((new_delay << 16) & 0x3f0000));
|
|
|
|
} else {
|
|
|
|
/* Make sure we continue to get down interrupts
|
|
|
|
* until we hit the minimum frequency */
|
|
|
|
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
|
|
|
|
I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
|
|
|
|
}
|
2011-04-25 12:25:20 -06:00
|
|
|
gen6_gt_force_wake_put(dev_priv);
|
2010-12-17 15:19:02 -07:00
|
|
|
}
|
|
|
|
|
2011-04-25 12:25:20 -06:00
|
|
|
gen6_set_rps(dev_priv->dev, new_delay);
|
2010-12-17 15:19:02 -07:00
|
|
|
dev_priv->cur_delay = new_delay;
|
|
|
|
|
2011-04-25 12:25:20 -06:00
|
|
|
/*
|
|
|
|
* rps_lock not held here because clearing is non-destructive. There is
|
|
|
|
* an *extremely* unlikely race with gen6_rps_enable() that is prevented
|
|
|
|
* by holding struct_mutex for the duration of the write.
|
|
|
|
*/
|
|
|
|
mutex_unlock(&dev_priv->dev->struct_mutex);
|
2010-12-17 15:19:02 -07:00
|
|
|
}
|
|
|
|
|
2011-01-04 16:09:39 -07:00
|
|
|
static void pch_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
u32 pch_iir;
|
2011-02-07 13:26:52 -07:00
|
|
|
int pipe;
|
2011-01-04 16:09:39 -07:00
|
|
|
|
|
|
|
pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_POWER_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
|
|
|
|
(pch_iir & SDE_AUDIO_POWER_MASK) >>
|
|
|
|
SDE_AUDIO_POWER_SHIFT);
|
|
|
|
|
|
|
|
if (pch_iir & SDE_GMBUS)
|
|
|
|
DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_HDCP_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_TRANS_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_POISON)
|
|
|
|
DRM_ERROR("PCH poison interrupt\n");
|
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
if (pch_iir & SDE_FDI_MASK)
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(FDI_RX_IIR(pipe)));
|
2011-01-04 16:09:39 -07:00
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
|
|
|
|
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
|
2011-04-06 13:13:38 -06:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
int ret = IRQ_NONE;
|
|
|
|
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
|
|
|
|
struct drm_i915_master_private *master_priv;
|
|
|
|
|
|
|
|
atomic_inc(&dev_priv->irq_received);
|
|
|
|
|
|
|
|
/* disable master interrupt before clearing iir */
|
|
|
|
de_ier = I915_READ(DEIER);
|
|
|
|
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ(DEIER);
|
|
|
|
|
|
|
|
de_iir = I915_READ(DEIIR);
|
|
|
|
gt_iir = I915_READ(GTIIR);
|
|
|
|
pch_iir = I915_READ(SDEIIR);
|
|
|
|
pm_iir = I915_READ(GEN6_PMIIR);
|
|
|
|
|
|
|
|
if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
|
|
|
if (dev->primary->master) {
|
|
|
|
master_priv = dev->primary->master->driver_priv;
|
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->last_dispatch =
|
|
|
|
READ_BREADCRUMB(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
|
|
|
if (gt_iir & GT_BLT_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[BCS]);
|
|
|
|
|
|
|
|
if (de_iir & DE_GSE_IVB)
|
|
|
|
intel_opregion_gse_intr(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
|
|
|
|
intel_prepare_page_flip(dev, 0);
|
|
|
|
intel_finish_page_flip_plane(dev, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
|
|
|
|
intel_prepare_page_flip(dev, 1);
|
|
|
|
intel_finish_page_flip_plane(dev, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (de_iir & DE_PIPEA_VBLANK_IVB)
|
|
|
|
drm_handle_vblank(dev, 0);
|
|
|
|
|
2011-05-25 03:56:56 -06:00
|
|
|
if (de_iir & DE_PIPEB_VBLANK_IVB)
|
2011-04-06 13:13:38 -06:00
|
|
|
drm_handle_vblank(dev, 1);
|
|
|
|
|
|
|
|
/* check event from PCH */
|
|
|
|
if (de_iir & DE_PCH_EVENT_IVB) {
|
|
|
|
if (pch_iir & SDE_HOTPLUG_MASK_CPT)
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->hotplug_work);
|
|
|
|
pch_irq_handler(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
|
|
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dev_priv->rps_lock, flags);
|
|
|
|
WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
|
|
|
|
dev_priv->pm_iir |= pm_iir;
|
2011-09-08 06:00:20 -06:00
|
|
|
I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
|
|
|
|
POSTING_READ(GEN6_PMIMR);
|
2011-04-06 13:13:38 -06:00
|
|
|
spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->rps_work);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* should clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
I915_WRITE(DEIIR, de_iir);
|
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
|
|
|
|
|
|
|
done:
|
|
|
|
I915_WRITE(DEIER, de_ier);
|
|
|
|
POSTING_READ(DEIER);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
2011-04-07 14:53:55 -06:00
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2009-06-08 00:40:19 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
int ret = IRQ_NONE;
|
2010-12-17 15:19:02 -07:00
|
|
|
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
|
2010-10-08 03:21:06 -06:00
|
|
|
u32 hotplug_mask;
|
2009-06-08 00:40:19 -06:00
|
|
|
struct drm_i915_master_private *master_priv;
|
2010-09-19 07:40:43 -06:00
|
|
|
u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
|
|
|
|
|
2011-04-07 14:53:55 -06:00
|
|
|
atomic_inc(&dev_priv->irq_received);
|
|
|
|
|
2010-09-19 07:40:43 -06:00
|
|
|
if (IS_GEN6(dev))
|
|
|
|
bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2009-11-05 19:13:01 -07:00
|
|
|
/* disable master interrupt before clearing iir */
|
|
|
|
de_ier = I915_READ(DEIER);
|
|
|
|
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIER);
|
2009-11-05 19:13:01 -07:00
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
de_iir = I915_READ(DEIIR);
|
|
|
|
gt_iir = I915_READ(GTIIR);
|
2009-11-03 11:57:21 -07:00
|
|
|
pch_iir = I915_READ(SDEIIR);
|
2010-12-17 15:19:02 -07:00
|
|
|
pm_iir = I915_READ(GEN6_PMIIR);
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-12-17 15:19:02 -07:00
|
|
|
if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
|
|
|
|
(!IS_GEN6(dev) || pm_iir == 0))
|
2010-01-14 19:29:06 -07:00
|
|
|
goto done;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-10-08 03:21:06 -06:00
|
|
|
if (HAS_PCH_CPT(dev))
|
|
|
|
hotplug_mask = SDE_HOTPLUG_MASK_CPT;
|
|
|
|
else
|
|
|
|
hotplug_mask = SDE_HOTPLUG_MASK;
|
|
|
|
|
2010-01-14 19:29:06 -07:00
|
|
|
ret = IRQ_HANDLED;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-01-14 19:29:06 -07:00
|
|
|
if (dev->primary->master) {
|
|
|
|
master_priv = dev->primary->master->driver_priv;
|
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->last_dispatch =
|
|
|
|
READ_BREADCRUMB(dev_priv);
|
|
|
|
}
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-12-15 02:56:50 -07:00
|
|
|
if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
|
2010-12-04 04:30:53 -07:00
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
2010-09-19 07:40:43 -06:00
|
|
|
if (gt_iir & bsd_usr_interrupt)
|
2010-12-04 04:30:53 -07:00
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
|
|
|
if (gt_iir & GT_BLT_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[BCS]);
|
2009-10-27 23:10:00 -06:00
|
|
|
|
2010-01-14 19:29:06 -07:00
|
|
|
if (de_iir & DE_GSE)
|
2010-08-24 02:02:58 -06:00
|
|
|
intel_opregion_gse_intr(dev);
|
2009-11-03 11:57:21 -07:00
|
|
|
|
2010-02-08 18:46:19 -07:00
|
|
|
if (de_iir & DE_PLANEA_FLIP_DONE) {
|
2010-01-29 12:18:31 -07:00
|
|
|
intel_prepare_page_flip(dev, 0);
|
2010-09-02 10:59:39 -06:00
|
|
|
intel_finish_page_flip_plane(dev, 0);
|
2010-02-08 18:46:19 -07:00
|
|
|
}
|
2010-01-29 12:18:31 -07:00
|
|
|
|
2010-02-08 18:46:19 -07:00
|
|
|
if (de_iir & DE_PLANEB_FLIP_DONE) {
|
2010-01-29 12:18:31 -07:00
|
|
|
intel_prepare_page_flip(dev, 1);
|
2010-09-02 10:59:39 -06:00
|
|
|
intel_finish_page_flip_plane(dev, 1);
|
2010-02-08 18:46:19 -07:00
|
|
|
}
|
2010-01-29 12:18:31 -07:00
|
|
|
|
2010-02-08 18:46:19 -07:00
|
|
|
if (de_iir & DE_PIPEA_VBLANK)
|
2010-01-22 09:12:58 -07:00
|
|
|
drm_handle_vblank(dev, 0);
|
|
|
|
|
2010-02-08 18:46:19 -07:00
|
|
|
if (de_iir & DE_PIPEB_VBLANK)
|
2010-01-22 09:12:58 -07:00
|
|
|
drm_handle_vblank(dev, 1);
|
|
|
|
|
2010-01-14 19:29:06 -07:00
|
|
|
/* check event from PCH */
|
2011-01-04 16:09:39 -07:00
|
|
|
if (de_iir & DE_PCH_EVENT) {
|
|
|
|
if (pch_iir & hotplug_mask)
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->hotplug_work);
|
|
|
|
pch_irq_handler(dev);
|
|
|
|
}
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-01-29 12:27:07 -07:00
|
|
|
if (de_iir & DE_PCU_EVENT) {
|
2010-05-20 15:28:11 -06:00
|
|
|
I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
|
2010-01-29 12:27:07 -07:00
|
|
|
i915_handle_rps_change(dev);
|
|
|
|
}
|
|
|
|
|
2011-04-25 12:25:20 -06:00
|
|
|
if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
|
|
|
|
/*
|
|
|
|
* IIR bits should never already be set because IMR should
|
|
|
|
* prevent an interrupt from being shown in IIR. The warning
|
|
|
|
* displays a case where we've unsafely cleared
|
|
|
|
* dev_priv->pm_iir. Although missing an interrupt of the same
|
|
|
|
* type is not a problem, it displays a problem in the logic.
|
|
|
|
*
|
|
|
|
* The mask bit in IMR is cleared by rps_work.
|
|
|
|
*/
|
|
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dev_priv->rps_lock, flags);
|
|
|
|
WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
|
|
|
|
dev_priv->pm_iir |= pm_iir;
|
2011-09-08 06:00:20 -06:00
|
|
|
I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
|
|
|
|
POSTING_READ(GEN6_PMIMR);
|
2011-04-25 12:25:20 -06:00
|
|
|
spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->rps_work);
|
|
|
|
}
|
2010-12-17 15:19:02 -07:00
|
|
|
|
2010-01-14 19:29:06 -07:00
|
|
|
/* should clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
I915_WRITE(DEIIR, de_iir);
|
2011-04-25 12:25:20 -06:00
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
2010-01-14 19:29:06 -07:00
|
|
|
|
|
|
|
done:
|
2009-11-05 19:13:01 -07:00
|
|
|
I915_WRITE(DEIER, de_ier);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIER);
|
2009-11-05 19:13:01 -07:00
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-07-11 14:48:03 -06:00
|
|
|
/**
|
|
|
|
* i915_error_work_func - do process context error handling work
|
|
|
|
* @work: work struct
|
|
|
|
*
|
|
|
|
* Fire an error uevent so userspace can see that a hang or error
|
|
|
|
* was detected.
|
|
|
|
*/
|
|
|
|
static void i915_error_work_func(struct work_struct *work)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
|
|
|
|
error_work);
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2009-09-14 15:48:46 -06:00
|
|
|
char *error_event[] = { "ERROR=1", NULL };
|
|
|
|
char *reset_event[] = { "RESET=1", NULL };
|
|
|
|
char *reset_done_event[] = { "ERROR=0", NULL };
|
2009-07-11 14:48:03 -06:00
|
|
|
|
2009-09-14 15:48:46 -06:00
|
|
|
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
|
|
|
|
|
2009-09-14 15:48:47 -06:00
|
|
|
if (atomic_read(&dev_priv->mm.wedged)) {
|
2010-09-19 05:38:26 -06:00
|
|
|
DRM_DEBUG_DRIVER("resetting chip\n");
|
|
|
|
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
|
|
|
|
if (!i915_reset(dev, GRDOM_RENDER)) {
|
|
|
|
atomic_set(&dev_priv->mm.wedged, 0);
|
|
|
|
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
|
2009-09-14 15:48:46 -06:00
|
|
|
}
|
2010-09-25 03:19:17 -06:00
|
|
|
complete_all(&dev_priv->error_completion);
|
2009-09-14 15:48:46 -06:00
|
|
|
}
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
|
2010-08-19 01:19:30 -06:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
2010-02-18 03:24:56 -07:00
|
|
|
static struct drm_i915_error_object *
|
2011-01-07 14:06:07 -07:00
|
|
|
i915_error_object_create(struct drm_i915_private *dev_priv,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *src)
|
2010-02-18 03:24:56 -07:00
|
|
|
{
|
|
|
|
struct drm_i915_error_object *dst;
|
|
|
|
int page, page_count;
|
2010-08-07 04:01:26 -06:00
|
|
|
u32 reloc_offset;
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (src == NULL || src->pages == NULL)
|
2010-02-18 03:24:56 -07:00
|
|
|
return NULL;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
page_count = src->base.size / PAGE_SIZE;
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2011-08-16 13:34:10 -06:00
|
|
|
dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
|
2010-02-18 03:24:56 -07:00
|
|
|
if (dst == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
reloc_offset = src->gtt_offset;
|
2010-02-18 03:24:56 -07:00
|
|
|
for (page = 0; page < page_count; page++) {
|
2010-05-11 15:07:05 -06:00
|
|
|
unsigned long flags;
|
2010-08-07 04:01:26 -06:00
|
|
|
void __iomem *s;
|
|
|
|
void *d;
|
2010-05-11 15:07:05 -06:00
|
|
|
|
2010-08-07 04:01:26 -06:00
|
|
|
d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
|
2010-02-18 03:24:56 -07:00
|
|
|
if (d == NULL)
|
|
|
|
goto unwind;
|
2010-08-07 04:01:26 -06:00
|
|
|
|
2010-05-11 15:07:05 -06:00
|
|
|
local_irq_save(flags);
|
2010-08-07 04:01:26 -06:00
|
|
|
s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
|
2010-10-26 15:21:51 -06:00
|
|
|
reloc_offset);
|
2010-08-07 04:01:26 -06:00
|
|
|
memcpy_fromio(d, s, PAGE_SIZE);
|
2010-10-26 15:21:51 -06:00
|
|
|
io_mapping_unmap_atomic(s);
|
2010-05-11 15:07:05 -06:00
|
|
|
local_irq_restore(flags);
|
2010-08-07 04:01:26 -06:00
|
|
|
|
2010-02-18 03:24:56 -07:00
|
|
|
dst->pages[page] = d;
|
2010-08-07 04:01:26 -06:00
|
|
|
|
|
|
|
reloc_offset += PAGE_SIZE;
|
2010-02-18 03:24:56 -07:00
|
|
|
}
|
|
|
|
dst->page_count = page_count;
|
2010-11-08 12:18:58 -07:00
|
|
|
dst->gtt_offset = src->gtt_offset;
|
2010-02-18 03:24:56 -07:00
|
|
|
|
|
|
|
return dst;
|
|
|
|
|
|
|
|
unwind:
|
|
|
|
while (page--)
|
|
|
|
kfree(dst->pages[page]);
|
|
|
|
kfree(dst);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_error_object_free(struct drm_i915_error_object *obj)
|
|
|
|
{
|
|
|
|
int page;
|
|
|
|
|
|
|
|
if (obj == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (page = 0; page < obj->page_count; page++)
|
|
|
|
kfree(obj->pages[page]);
|
|
|
|
|
|
|
|
kfree(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_error_state_free(struct drm_device *dev,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
2011-01-27 12:15:11 -07:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
|
|
|
|
i915_error_object_free(error->batchbuffer[i]);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
|
|
|
|
i915_error_object_free(error->ringbuffer[i]);
|
|
|
|
|
2010-02-18 03:24:56 -07:00
|
|
|
kfree(error->active_bo);
|
2010-08-04 13:26:07 -06:00
|
|
|
kfree(error->overlay);
|
2010-02-18 03:24:56 -07:00
|
|
|
kfree(error);
|
|
|
|
}
|
|
|
|
|
2010-11-22 01:07:02 -07:00
|
|
|
static u32 capture_bo_list(struct drm_i915_error_buffer *err,
|
|
|
|
int count,
|
|
|
|
struct list_head *head)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
list_for_each_entry(obj, head, mm_list) {
|
|
|
|
err->size = obj->base.size;
|
|
|
|
err->name = obj->base.name;
|
|
|
|
err->seqno = obj->last_rendering_seqno;
|
|
|
|
err->gtt_offset = obj->gtt_offset;
|
|
|
|
err->read_domains = obj->base.read_domains;
|
|
|
|
err->write_domain = obj->base.write_domain;
|
|
|
|
err->fence_reg = obj->fence_reg;
|
|
|
|
err->pinned = 0;
|
|
|
|
if (obj->pin_count > 0)
|
|
|
|
err->pinned = 1;
|
|
|
|
if (obj->user_pin_count > 0)
|
|
|
|
err->pinned = -1;
|
|
|
|
err->tiling = obj->tiling_mode;
|
|
|
|
err->dirty = obj->dirty;
|
|
|
|
err->purgeable = obj->madv != I915_MADV_WILLNEED;
|
2011-12-14 05:57:00 -07:00
|
|
|
err->ring = obj->ring ? obj->ring->id : -1;
|
2011-03-29 17:59:50 -06:00
|
|
|
err->cache_level = obj->cache_level;
|
2010-11-22 01:07:02 -07:00
|
|
|
|
|
|
|
if (++i == count)
|
|
|
|
break;
|
|
|
|
|
|
|
|
err++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2010-10-24 03:28:47 -06:00
|
|
|
static void i915_gem_record_fences(struct drm_device *dev,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Fences */
|
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
2011-10-09 13:52:01 -06:00
|
|
|
case 7:
|
2010-10-24 03:28:47 -06:00
|
|
|
case 6:
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
case 4:
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
|
|
|
|
case 2:
|
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
|
|
|
|
break;
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-07 14:06:07 -07:00
|
|
|
static struct drm_i915_error_object *
|
|
|
|
i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
u32 seqno;
|
|
|
|
|
|
|
|
if (!ring->get_seqno)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
seqno = ring->get_seqno(ring);
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
|
|
|
|
if (obj->ring != ring)
|
|
|
|
continue;
|
|
|
|
|
2011-01-12 13:33:01 -07:00
|
|
|
if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
|
2011-01-07 14:06:07 -07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* We need to copy these to an anonymous buffer as the simplest
|
|
|
|
* method to avoid being overwritten by userspace.
|
|
|
|
*/
|
|
|
|
return i915_error_object_create(dev_priv, obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2011-12-14 05:57:01 -07:00
|
|
|
static void i915_record_ring_state(struct drm_device *dev,
|
|
|
|
struct drm_i915_error_state *error,
|
|
|
|
struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2011-12-14 05:57:39 -07:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2011-12-14 05:57:02 -07:00
|
|
|
error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
|
2011-12-14 05:57:39 -07:00
|
|
|
error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
|
|
|
|
}
|
2011-12-14 05:57:02 -07:00
|
|
|
|
2011-12-14 05:57:01 -07:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
|
|
error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
|
|
|
|
error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
|
|
|
|
error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
|
2011-12-14 05:57:02 -07:00
|
|
|
error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
|
2011-12-14 05:57:01 -07:00
|
|
|
if (ring->id == RCS) {
|
|
|
|
error->instdone1 = I915_READ(INSTDONE1);
|
|
|
|
error->bbaddr = I915_READ64(BB_ADDR);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
error->ipeir[ring->id] = I915_READ(IPEIR);
|
|
|
|
error->ipehr[ring->id] = I915_READ(IPEHR);
|
|
|
|
error->instdone[ring->id] = I915_READ(INSTDONE);
|
|
|
|
}
|
|
|
|
|
2011-12-14 05:57:02 -07:00
|
|
|
error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
|
2011-12-14 05:57:01 -07:00
|
|
|
error->seqno[ring->id] = ring->get_seqno(ring);
|
|
|
|
error->acthd[ring->id] = intel_ring_get_active_head(ring);
|
2011-12-14 05:57:02 -07:00
|
|
|
error->head[ring->id] = I915_READ_HEAD(ring);
|
|
|
|
error->tail[ring->id] = I915_READ_TAIL(ring);
|
2011-12-14 05:57:01 -07:00
|
|
|
}
|
|
|
|
|
2009-07-11 14:48:03 -06:00
|
|
|
/**
|
|
|
|
* i915_capture_error_state - capture an error record for later analysis
|
|
|
|
* @dev: drm device
|
|
|
|
*
|
|
|
|
* Should be called when an error is detected (either a hang or an error
|
|
|
|
* interrupt) to capture error state from the time of the error. Fills
|
|
|
|
* out a structure which becomes available in debugfs for user level tools
|
|
|
|
* to pick up.
|
|
|
|
*/
|
2009-06-18 17:56:52 -06:00
|
|
|
static void i915_capture_error_state(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2009-06-18 17:56:52 -06:00
|
|
|
struct drm_i915_error_state *error;
|
|
|
|
unsigned long flags;
|
2011-02-07 13:26:52 -07:00
|
|
|
int i, pipe;
|
2009-06-18 17:56:52 -06:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->error_lock, flags);
|
2010-02-18 03:24:56 -07:00
|
|
|
error = dev_priv->first_error;
|
|
|
|
spin_unlock_irqrestore(&dev_priv->error_lock, flags);
|
|
|
|
if (error)
|
|
|
|
return;
|
2009-06-18 17:56:52 -06:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
/* Account for pipe specific data like PIPE*STAT */
|
2011-12-14 05:57:39 -07:00
|
|
|
error = kzalloc(sizeof(*error), GFP_ATOMIC);
|
2009-06-18 17:56:52 -06:00
|
|
|
if (!error) {
|
2010-02-18 03:24:56 -07:00
|
|
|
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
|
|
|
|
return;
|
2009-06-18 17:56:52 -06:00
|
|
|
}
|
|
|
|
|
2011-02-01 07:15:55 -07:00
|
|
|
DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
|
|
|
|
dev->primary->index);
|
2010-10-01 06:23:27 -06:00
|
|
|
|
2009-06-18 17:56:52 -06:00
|
|
|
error->eir = I915_READ(EIR);
|
|
|
|
error->pgtbl_er = I915_READ(PGTBL_ER);
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
|
2011-12-14 05:57:01 -07:00
|
|
|
|
2011-12-14 05:57:39 -07:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2010-10-27 13:36:41 -06:00
|
|
|
error->error = I915_READ(ERROR_GEN6);
|
2011-12-14 05:57:39 -07:00
|
|
|
error->done_reg = I915_READ(DONE_REG);
|
|
|
|
}
|
2011-12-14 05:57:01 -07:00
|
|
|
|
|
|
|
i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
|
|
|
|
if (HAS_BLT(dev))
|
|
|
|
i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
|
|
|
|
if (HAS_BSD(dev))
|
|
|
|
i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
|
2010-10-29 12:00:51 -06:00
|
|
|
|
2010-10-24 03:28:47 -06:00
|
|
|
i915_gem_record_fences(dev, error);
|
2009-06-18 17:56:52 -06:00
|
|
|
|
2011-01-27 12:15:11 -07:00
|
|
|
/* Record the active batch and ring buffers */
|
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
2011-01-07 14:06:07 -07:00
|
|
|
error->batchbuffer[i] =
|
|
|
|
i915_error_first_batchbuffer(dev_priv,
|
|
|
|
&dev_priv->ring[i]);
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2011-01-27 12:15:11 -07:00
|
|
|
error->ringbuffer[i] =
|
|
|
|
i915_error_object_create(dev_priv,
|
|
|
|
dev_priv->ring[i].obj);
|
|
|
|
}
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2010-11-22 01:07:02 -07:00
|
|
|
/* Record buffers on the active and pinned lists. */
|
2010-02-18 03:24:56 -07:00
|
|
|
error->active_bo = NULL;
|
2010-11-22 01:07:02 -07:00
|
|
|
error->pinned_bo = NULL;
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2011-01-07 14:06:07 -07:00
|
|
|
i = 0;
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
|
|
|
|
i++;
|
|
|
|
error->active_bo_count = i;
|
2010-11-08 12:18:58 -07:00
|
|
|
list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
|
2011-01-07 14:06:07 -07:00
|
|
|
i++;
|
|
|
|
error->pinned_bo_count = i - error->active_bo_count;
|
2010-11-22 01:07:02 -07:00
|
|
|
|
2011-01-24 05:34:00 -07:00
|
|
|
error->active_bo = NULL;
|
|
|
|
error->pinned_bo = NULL;
|
2011-01-07 14:06:07 -07:00
|
|
|
if (i) {
|
|
|
|
error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
|
2010-02-18 03:24:56 -07:00
|
|
|
GFP_ATOMIC);
|
2010-11-22 01:07:02 -07:00
|
|
|
if (error->active_bo)
|
|
|
|
error->pinned_bo =
|
|
|
|
error->active_bo + error->active_bo_count;
|
2010-02-18 03:24:56 -07:00
|
|
|
}
|
|
|
|
|
2010-11-22 01:07:02 -07:00
|
|
|
if (error->active_bo)
|
|
|
|
error->active_bo_count =
|
|
|
|
capture_bo_list(error->active_bo,
|
|
|
|
error->active_bo_count,
|
|
|
|
&dev_priv->mm.active_list);
|
|
|
|
|
|
|
|
if (error->pinned_bo)
|
|
|
|
error->pinned_bo_count =
|
|
|
|
capture_bo_list(error->pinned_bo,
|
|
|
|
error->pinned_bo_count,
|
|
|
|
&dev_priv->mm.pinned_list);
|
|
|
|
|
2010-02-18 03:24:56 -07:00
|
|
|
do_gettimeofday(&error->time);
|
|
|
|
|
2010-08-04 13:26:07 -06:00
|
|
|
error->overlay = intel_overlay_capture_error_state(dev);
|
2010-11-21 06:12:35 -07:00
|
|
|
error->display = intel_display_capture_error_state(dev);
|
2010-08-04 13:26:07 -06:00
|
|
|
|
2010-02-18 03:24:56 -07:00
|
|
|
spin_lock_irqsave(&dev_priv->error_lock, flags);
|
|
|
|
if (dev_priv->first_error == NULL) {
|
|
|
|
dev_priv->first_error = error;
|
|
|
|
error = NULL;
|
|
|
|
}
|
2009-06-18 17:56:52 -06:00
|
|
|
spin_unlock_irqrestore(&dev_priv->error_lock, flags);
|
2010-02-18 03:24:56 -07:00
|
|
|
|
|
|
|
if (error)
|
|
|
|
i915_error_state_free(dev, error);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_destroy_error_state(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_error_state *error;
|
2012-01-23 16:30:02 -07:00
|
|
|
unsigned long flags;
|
2010-02-18 03:24:56 -07:00
|
|
|
|
2012-01-23 16:30:02 -07:00
|
|
|
spin_lock_irqsave(&dev_priv->error_lock, flags);
|
2010-02-18 03:24:56 -07:00
|
|
|
error = dev_priv->first_error;
|
|
|
|
dev_priv->first_error = NULL;
|
2012-01-23 16:30:02 -07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->error_lock, flags);
|
2010-02-18 03:24:56 -07:00
|
|
|
|
|
|
|
if (error)
|
|
|
|
i915_error_state_free(dev, error);
|
2009-06-18 17:56:52 -06:00
|
|
|
}
|
2010-08-19 01:19:30 -06:00
|
|
|
#else
|
|
|
|
#define i915_capture_error_state(x)
|
|
|
|
#endif
|
2009-06-18 17:56:52 -06:00
|
|
|
|
2010-05-27 06:18:12 -06:00
|
|
|
static void i915_report_and_clear_eir(struct drm_device *dev)
|
2009-07-11 14:48:03 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 eir = I915_READ(EIR);
|
2011-02-07 13:26:52 -07:00
|
|
|
int pipe;
|
2009-07-11 14:48:03 -06:00
|
|
|
|
2010-05-27 06:18:12 -06:00
|
|
|
if (!eir)
|
|
|
|
return;
|
2009-07-11 14:48:03 -06:00
|
|
|
|
|
|
|
printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
|
|
|
|
eir);
|
|
|
|
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
|
|
I915_READ(IPEIR_I965));
|
|
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
|
|
I915_READ(IPEHR_I965));
|
|
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
|
|
I915_READ(INSTDONE_I965));
|
|
|
|
printk(KERN_ERR " INSTPS: 0x%08x\n",
|
|
|
|
I915_READ(INSTPS));
|
|
|
|
printk(KERN_ERR " INSTDONE1: 0x%08x\n",
|
|
|
|
I915_READ(INSTDONE1));
|
|
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
|
|
I915_READ(ACTHD_I965));
|
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
if (eir & GM45_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
|
|
|
printk(KERN_ERR "page table error\n");
|
|
|
|
printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
|
|
|
|
pgtbl_err);
|
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-16 17:32:17 -06:00
|
|
|
if (!IS_GEN2(dev)) {
|
2009-07-11 14:48:03 -06:00
|
|
|
if (eir & I915_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
|
|
|
printk(KERN_ERR "page table error\n");
|
|
|
|
printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
|
|
|
|
pgtbl_err);
|
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eir & I915_ERROR_MEMORY_REFRESH) {
|
2011-02-07 13:26:52 -07:00
|
|
|
printk(KERN_ERR "memory refresh error:\n");
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
printk(KERN_ERR "pipe %c stat: 0x%08x\n",
|
|
|
|
pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
|
2009-07-11 14:48:03 -06:00
|
|
|
/* pipestat has already been acked */
|
|
|
|
}
|
|
|
|
if (eir & I915_ERROR_INSTRUCTION) {
|
|
|
|
printk(KERN_ERR "instruction error\n");
|
|
|
|
printk(KERN_ERR " INSTPM: 0x%08x\n",
|
|
|
|
I915_READ(INSTPM));
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
2009-07-11 14:48:03 -06:00
|
|
|
u32 ipeir = I915_READ(IPEIR);
|
|
|
|
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
|
|
I915_READ(IPEIR));
|
|
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
|
|
I915_READ(IPEHR));
|
|
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
|
|
I915_READ(INSTDONE));
|
|
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
|
|
I915_READ(ACTHD));
|
|
|
|
I915_WRITE(IPEIR, ipeir);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(IPEIR);
|
2009-07-11 14:48:03 -06:00
|
|
|
} else {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
|
|
|
printk(KERN_ERR " IPEIR: 0x%08x\n",
|
|
|
|
I915_READ(IPEIR_I965));
|
|
|
|
printk(KERN_ERR " IPEHR: 0x%08x\n",
|
|
|
|
I915_READ(IPEHR_I965));
|
|
|
|
printk(KERN_ERR " INSTDONE: 0x%08x\n",
|
|
|
|
I915_READ(INSTDONE_I965));
|
|
|
|
printk(KERN_ERR " INSTPS: 0x%08x\n",
|
|
|
|
I915_READ(INSTPS));
|
|
|
|
printk(KERN_ERR " INSTDONE1: 0x%08x\n",
|
|
|
|
I915_READ(INSTDONE1));
|
|
|
|
printk(KERN_ERR " ACTHD: 0x%08x\n",
|
|
|
|
I915_READ(ACTHD_I965));
|
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(EIR, eir);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(EIR);
|
2009-07-11 14:48:03 -06:00
|
|
|
eir = I915_READ(EIR);
|
|
|
|
if (eir) {
|
|
|
|
/*
|
|
|
|
* some errors might have become stuck,
|
|
|
|
* mask them.
|
|
|
|
*/
|
|
|
|
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
|
|
|
|
I915_WRITE(EMR, I915_READ(EMR) | eir);
|
|
|
|
I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
}
|
2010-05-27 06:18:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_handle_error - handle an error interrupt
|
|
|
|
* @dev: drm device
|
|
|
|
*
|
|
|
|
* Do some basic checking of regsiter state at error interrupt time and
|
|
|
|
* dump it to the syslog. Also call i915_capture_error_state() to make
|
|
|
|
* sure we get a record and make it available in debugfs. Fire a uevent
|
|
|
|
* so userspace knows something bad happened (should trigger collection
|
|
|
|
* of a ring dump etc.).
|
|
|
|
*/
|
2010-11-10 18:16:58 -07:00
|
|
|
void i915_handle_error(struct drm_device *dev, bool wedged)
|
2010-05-27 06:18:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
i915_capture_error_state(dev);
|
|
|
|
i915_report_and_clear_eir(dev);
|
2009-07-11 14:48:03 -06:00
|
|
|
|
2009-09-14 15:48:47 -06:00
|
|
|
if (wedged) {
|
2010-09-25 03:19:17 -06:00
|
|
|
INIT_COMPLETION(dev_priv->error_completion);
|
2009-09-14 15:48:47 -06:00
|
|
|
atomic_set(&dev_priv->mm.wedged, 1);
|
|
|
|
|
2009-09-14 15:48:45 -06:00
|
|
|
/*
|
|
|
|
* Wakeup waiting processes so they don't hang
|
|
|
|
*/
|
2010-12-04 04:30:53 -07:00
|
|
|
wake_up_all(&dev_priv->ring[RCS].irq_queue);
|
2010-09-24 09:02:42 -06:00
|
|
|
if (HAS_BSD(dev))
|
2010-12-04 04:30:53 -07:00
|
|
|
wake_up_all(&dev_priv->ring[VCS].irq_queue);
|
2010-10-19 04:19:32 -06:00
|
|
|
if (HAS_BLT(dev))
|
2010-12-04 04:30:53 -07:00
|
|
|
wake_up_all(&dev_priv->ring[BCS].irq_queue);
|
2009-09-14 15:48:45 -06:00
|
|
|
}
|
|
|
|
|
2009-08-03 17:09:16 -06:00
|
|
|
queue_work(dev_priv->wq, &dev_priv->error_work);
|
2009-07-11 14:48:03 -06:00
|
|
|
}
|
|
|
|
|
2010-09-01 10:47:52 -06:00
|
|
|
static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-01 10:47:52 -06:00
|
|
|
struct intel_unpin_work *work;
|
|
|
|
unsigned long flags;
|
|
|
|
bool stall_detected;
|
|
|
|
|
|
|
|
/* Ignore early vblank irqs */
|
|
|
|
if (intel_crtc == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
work = intel_crtc->unpin_work;
|
|
|
|
|
|
|
|
if (work == NULL || work->pending || !work->enable_stall_check) {
|
|
|
|
/* Either the pending flip IRQ arrived, or we're too early. Don't check */
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = work->pending_flip_obj;
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
2011-02-07 13:26:52 -07:00
|
|
|
int dspsurf = DSPSURF(intel_crtc->plane);
|
2010-11-08 12:18:58 -07:00
|
|
|
stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
|
2010-09-01 10:47:52 -06:00
|
|
|
} else {
|
2011-02-07 13:26:52 -07:00
|
|
|
int dspaddr = DSPADDR(intel_crtc->plane);
|
2010-11-08 12:18:58 -07:00
|
|
|
stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
|
2011-12-19 15:06:49 -07:00
|
|
|
crtc->y * crtc->fb->pitches[0] +
|
2010-09-01 10:47:52 -06:00
|
|
|
crtc->x * crtc->fb->bits_per_pixel/8);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
|
|
|
if (stall_detected) {
|
|
|
|
DRM_DEBUG_DRIVER("Pageflip stall detected\n");
|
|
|
|
intel_prepare_page_flip(dev, intel_crtc->plane);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2007-07-10 23:53:27 -06:00
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2005-04-16 16:20:36 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2008-11-27 21:22:24 -07:00
|
|
|
struct drm_i915_master_private *master_priv;
|
2008-11-04 16:50:30 -07:00
|
|
|
u32 iir, new_iir;
|
2011-02-07 13:26:52 -07:00
|
|
|
u32 pipe_stats[I915_MAX_PIPES];
|
2008-11-19 15:03:05 -07:00
|
|
|
u32 vblank_status;
|
2008-09-30 13:14:26 -06:00
|
|
|
int vblank = 0;
|
2008-11-04 03:03:27 -07:00
|
|
|
unsigned long irqflags;
|
2008-11-19 15:03:05 -07:00
|
|
|
int irq_received;
|
2011-02-07 13:26:52 -07:00
|
|
|
int ret = IRQ_NONE, pipe;
|
|
|
|
bool blc_event = false;
|
2006-03-20 00:34:29 -07:00
|
|
|
|
2008-10-06 16:14:12 -06:00
|
|
|
atomic_inc(&dev_priv->irq_received);
|
|
|
|
|
2008-07-29 13:10:39 -06:00
|
|
|
iir = I915_READ(IIR);
|
2006-10-24 07:37:43 -06:00
|
|
|
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2010-06-30 14:16:00 -06:00
|
|
|
vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
|
2010-06-30 14:15:19 -06:00
|
|
|
else
|
2010-06-30 14:16:00 -06:00
|
|
|
vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
|
2008-05-06 20:15:39 -06:00
|
|
|
|
2008-11-19 15:03:05 -07:00
|
|
|
for (;;) {
|
|
|
|
irq_received = iir != 0;
|
|
|
|
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2009-07-11 14:48:03 -06:00
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2009-09-14 15:48:47 -06:00
|
|
|
i915_handle_error(dev, false);
|
2009-07-11 14:48:03 -06:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
|
|
|
if (pipe_stats[pipe] & 0x8000ffff) {
|
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
|
|
|
|
DRM_DEBUG_DRIVER("pipe %c underrun\n",
|
|
|
|
pipe_name(pipe));
|
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
|
|
|
irq_received = 1;
|
|
|
|
}
|
2008-11-04 16:50:30 -07:00
|
|
|
}
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2008-11-19 15:03:05 -07:00
|
|
|
|
|
|
|
if (!irq_received)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
2008-08-05 12:37:25 -06:00
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
|
|
|
if ((I915_HAS_HOTPLUG(dev)) &&
|
|
|
|
(iir & I915_DISPLAY_PORT_INTERRUPT)) {
|
|
|
|
u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
|
|
|
|
|
2009-10-08 21:39:40 -06:00
|
|
|
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
|
2009-03-31 15:11:15 -06:00
|
|
|
hotplug_status);
|
|
|
|
if (hotplug_status & dev_priv->hotplug_supported_mask)
|
2009-08-03 17:09:16 -06:00
|
|
|
queue_work(dev_priv->wq,
|
|
|
|
&dev_priv->hotplug_work);
|
2009-03-31 15:11:15 -06:00
|
|
|
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
|
|
|
|
I915_READ(PORT_HOTPLUG_STAT);
|
|
|
|
}
|
|
|
|
|
2008-11-04 16:50:30 -07:00
|
|
|
I915_WRITE(IIR, iir);
|
|
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
2008-11-04 03:03:27 -07:00
|
|
|
|
2008-11-27 21:22:24 -07:00
|
|
|
if (dev->primary->master) {
|
|
|
|
master_priv = dev->primary->master->driver_priv;
|
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->last_dispatch =
|
|
|
|
READ_BREADCRUMB(dev_priv);
|
|
|
|
}
|
2008-09-30 13:14:26 -06:00
|
|
|
|
2010-10-19 04:19:32 -06:00
|
|
|
if (iir & I915_USER_INTERRUPT)
|
2010-12-04 04:30:53 -07:00
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
if (iir & I915_BSD_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
2010-05-20 19:08:57 -06:00
|
|
|
|
2010-03-26 11:35:20 -06:00
|
|
|
if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
|
2009-11-18 09:25:18 -07:00
|
|
|
intel_prepare_page_flip(dev, 0);
|
2010-03-26 11:35:20 -06:00
|
|
|
if (dev_priv->flip_pending_is_done)
|
|
|
|
intel_finish_page_flip_plane(dev, 0);
|
|
|
|
}
|
2009-11-18 09:25:18 -07:00
|
|
|
|
2010-03-26 11:35:20 -06:00
|
|
|
if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
|
2010-07-01 05:45:43 -06:00
|
|
|
intel_prepare_page_flip(dev, 1);
|
2010-03-26 11:35:20 -06:00
|
|
|
if (dev_priv->flip_pending_is_done)
|
|
|
|
intel_finish_page_flip_plane(dev, 1);
|
|
|
|
}
|
2009-11-18 09:25:18 -07:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
if (pipe_stats[pipe] & vblank_status &&
|
|
|
|
drm_handle_vblank(dev, pipe)) {
|
|
|
|
vblank++;
|
|
|
|
if (!dev_priv->flip_pending_is_done) {
|
|
|
|
i915_pageflip_stall_check(dev, pipe);
|
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
}
|
2010-09-01 10:47:52 -06:00
|
|
|
}
|
2008-11-04 03:03:27 -07:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
|
|
|
|
blc_event = true;
|
2008-11-04 16:50:30 -07:00
|
|
|
}
|
2008-11-04 03:03:27 -07:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
|
|
|
|
if (blc_event || (iir & I915_ASLE_INTERRUPT))
|
2010-08-24 02:02:58 -06:00
|
|
|
intel_opregion_asle_intr(dev);
|
2008-11-04 16:50:30 -07:00
|
|
|
|
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
|
|
* transitions from zero to nonzero. If another bit got
|
|
|
|
* set while we were handling the existing iir bits, then
|
|
|
|
* we would never get another interrupt.
|
|
|
|
*
|
|
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
|
|
* we avoid exiting the interrupt handler only to generate
|
|
|
|
* another one.
|
|
|
|
*
|
|
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
|
|
* if an interrupt landed in the time between writing IIR and
|
|
|
|
* the posting read. This should be rare enough to never
|
|
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
|
|
* stray interrupts.
|
|
|
|
*/
|
|
|
|
iir = new_iir;
|
2008-11-19 15:03:05 -07:00
|
|
|
}
|
2008-09-30 13:14:26 -06:00
|
|
|
|
2008-11-19 15:03:05 -07:00
|
|
|
return ret;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-05-06 20:15:39 -06:00
|
|
|
static int i915_emit_irq(struct drm_device * dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2008-11-27 21:22:24 -07:00
|
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
|
2009-10-08 21:39:40 -06:00
|
|
|
DRM_DEBUG_DRIVER("\n");
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-08-20 09:20:13 -06:00
|
|
|
dev_priv->counter++;
|
2006-08-12 00:29:24 -06:00
|
|
|
if (dev_priv->counter > 0x7FFFFFFFUL)
|
2008-08-20 09:20:13 -06:00
|
|
|
dev_priv->counter = 1;
|
2008-11-27 21:22:24 -07:00
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->last_enqueue = dev_priv->counter;
|
2006-08-12 00:29:24 -06:00
|
|
|
|
2010-10-27 05:45:26 -06:00
|
|
|
if (BEGIN_LP_RING(4) == 0) {
|
|
|
|
OUT_RING(MI_STORE_DWORD_INDEX);
|
|
|
|
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
|
|
OUT_RING(dev_priv->counter);
|
|
|
|
OUT_RING(MI_USER_INTERRUPT);
|
|
|
|
ADVANCE_LP_RING();
|
|
|
|
}
|
2007-11-04 19:50:58 -07:00
|
|
|
|
2006-08-12 00:29:24 -06:00
|
|
|
return dev_priv->counter;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-07-10 23:53:27 -06:00
|
|
|
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2008-11-27 21:22:24 -07:00
|
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
2005-04-16 16:20:36 -06:00
|
|
|
int ret = 0;
|
2010-12-04 04:30:53 -07:00
|
|
|
struct intel_ring_buffer *ring = LP_RING(dev_priv);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-10-08 21:39:40 -06:00
|
|
|
DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
|
2005-04-16 16:20:36 -06:00
|
|
|
READ_BREADCRUMB(dev_priv));
|
|
|
|
|
2008-07-29 13:10:39 -06:00
|
|
|
if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
|
2008-11-27 21:22:24 -07:00
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
2008-07-29 13:10:39 -06:00
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-11-27 21:22:24 -07:00
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2010-12-13 09:54:50 -07:00
|
|
|
if (ring->irq_get(ring)) {
|
|
|
|
DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
|
|
|
|
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
|
|
|
ring->irq_put(ring);
|
2011-01-23 06:03:24 -07:00
|
|
|
} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
|
|
|
|
ret = -EBUSY;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-08-25 03:22:43 -06:00
|
|
|
if (ret == -EBUSY) {
|
2008-01-23 22:58:57 -07:00
|
|
|
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
2005-04-16 16:20:36 -06:00
|
|
|
READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
|
|
|
|
}
|
|
|
|
|
2008-05-06 20:15:39 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Needs the lock as it touches the ring.
|
|
|
|
*/
|
2007-09-02 20:06:45 -06:00
|
|
|
int i915_irq_emit(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2007-09-02 20:06:45 -06:00
|
|
|
drm_i915_irq_emit_t *emit = data;
|
2005-04-16 16:20:36 -06:00
|
|
|
int result;
|
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
|
2008-01-23 22:58:57 -07:00
|
|
|
DRM_ERROR("called with no initialization\n");
|
2007-08-25 03:22:43 -06:00
|
|
|
return -EINVAL;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2009-02-24 23:14:12 -07:00
|
|
|
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
|
2008-09-01 17:45:29 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2005-04-16 16:20:36 -06:00
|
|
|
result = i915_emit_irq(dev);
|
2008-09-01 17:45:29 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-09-02 20:06:45 -06:00
|
|
|
if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
|
2005-04-16 16:20:36 -06:00
|
|
|
DRM_ERROR("copy_to_user\n");
|
2007-08-25 03:22:43 -06:00
|
|
|
return -EFAULT;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Doesn't need the hardware lock.
|
|
|
|
*/
|
2007-09-02 20:06:45 -06:00
|
|
|
int i915_irq_wait(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2007-09-02 20:06:45 -06:00
|
|
|
drm_i915_irq_wait_t *irqwait = data;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
if (!dev_priv) {
|
2008-01-23 22:58:57 -07:00
|
|
|
DRM_ERROR("called with no initialization\n");
|
2007-08-25 03:22:43 -06:00
|
|
|
return -EINVAL;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-09-02 20:06:45 -06:00
|
|
|
return i915_wait_irq(dev, irqwait->irq_seq);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2008-10-18 20:39:29 -06:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 14:00:41 -06:00
|
|
|
static int i915_enable_vblank(struct drm_device *dev, int pipe)
|
2008-09-30 13:14:26 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2008-10-16 12:31:38 -06:00
|
|
|
unsigned long irqflags;
|
2009-01-08 11:42:15 -07:00
|
|
|
|
2010-09-11 06:48:45 -06:00
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
2009-01-08 11:42:15 -07:00
|
|
|
return -EINVAL;
|
2008-09-30 13:14:26 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2011-04-07 14:58:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2008-11-04 03:03:27 -07:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
|
|
|
PIPE_START_VBLANK_INTERRUPT_ENABLE);
|
2008-10-16 12:31:38 -06:00
|
|
|
else
|
2008-11-04 03:03:27 -07:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
|
|
|
PIPE_VBLANK_INTERRUPT_ENABLE);
|
2011-02-05 03:08:21 -07:00
|
|
|
|
|
|
|
/* maintain vblank delivery even in deep C-states */
|
|
|
|
if (dev_priv->info->gen == 3)
|
|
|
|
I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2011-02-05 03:08:21 -07:00
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
|
2011-04-07 14:58:17 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
|
2011-08-16 13:34:10 -06:00
|
|
|
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
|
2011-04-07 14:58:17 -06:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
|
2011-04-06 13:13:38 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
|
|
|
|
DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-18 20:39:29 -06:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 14:00:41 -06:00
|
|
|
static void i915_disable_vblank(struct drm_device *dev, int pipe)
|
2008-09-30 13:14:26 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2008-10-16 12:31:38 -06:00
|
|
|
unsigned long irqflags;
|
2008-09-30 13:14:26 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2011-02-05 03:08:21 -07:00
|
|
|
if (dev_priv->info->gen == 3)
|
|
|
|
I915_WRITE(INSTPM,
|
|
|
|
INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
|
|
|
|
|
2011-04-07 14:58:17 -06:00
|
|
|
i915_disable_pipestat(dev_priv, pipe,
|
|
|
|
PIPE_VBLANK_INTERRUPT_ENABLE |
|
|
|
|
PIPE_START_VBLANK_INTERRUPT_ENABLE);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
|
2011-04-07 14:58:17 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
|
2011-08-16 13:34:10 -06:00
|
|
|
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
|
2010-12-04 04:30:53 -07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2008-09-30 13:14:26 -06:00
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
|
2011-04-06 13:13:38 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
|
|
|
|
DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2006-06-24 01:07:34 -06:00
|
|
|
/* Set the vblank monitor pipe
|
|
|
|
*/
|
2007-09-02 20:06:45 -06:00
|
|
|
int i915_vblank_pipe_set(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
2006-06-24 01:07:34 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!dev_priv) {
|
2008-01-23 22:58:57 -07:00
|
|
|
DRM_ERROR("called with no initialization\n");
|
2007-08-25 03:22:43 -06:00
|
|
|
return -EINVAL;
|
2006-06-24 01:07:34 -06:00
|
|
|
}
|
|
|
|
|
2006-10-24 08:08:23 -06:00
|
|
|
return 0;
|
2006-06-24 01:07:34 -06:00
|
|
|
}
|
|
|
|
|
2007-09-02 20:06:45 -06:00
|
|
|
int i915_vblank_pipe_get(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
2006-06-24 01:07:34 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2007-09-02 20:06:45 -06:00
|
|
|
drm_i915_vblank_pipe_t *pipe = data;
|
2006-06-24 01:07:34 -06:00
|
|
|
|
|
|
|
if (!dev_priv) {
|
2008-01-23 22:58:57 -07:00
|
|
|
DRM_ERROR("called with no initialization\n");
|
2007-08-25 03:22:43 -06:00
|
|
|
return -EINVAL;
|
2006-06-24 01:07:34 -06:00
|
|
|
}
|
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
2007-09-02 20:06:45 -06:00
|
|
|
|
2006-06-24 01:07:34 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-10-24 07:37:43 -06:00
|
|
|
/**
|
|
|
|
* Schedule buffer swap at given vertical blank.
|
|
|
|
*/
|
2007-09-02 20:06:45 -06:00
|
|
|
int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
2006-10-24 07:37:43 -06:00
|
|
|
{
|
2008-11-04 13:01:24 -07:00
|
|
|
/* The delayed swap mechanism was fundamentally racy, and has been
|
|
|
|
* removed. The model was that the client requested a delayed flip/swap
|
|
|
|
* from the kernel, then waited for vblank before continuing to perform
|
|
|
|
* rendering. The problem was that the kernel might wake the client
|
|
|
|
* up before it dispatched the vblank swap (since the lock has to be
|
|
|
|
* held while touching the ringbuffer), in which case the client would
|
|
|
|
* clear and start the next frame before the swap occurred, and
|
|
|
|
* flicker would occur in addition to likely missing the vblank.
|
|
|
|
*
|
|
|
|
* In the absence of this ioctl, userland falls back to a correct path
|
|
|
|
* of waiting for a vblank, then dispatching the swap on its own.
|
|
|
|
* Context switching to userland and back is plenty fast enough for
|
|
|
|
* meeting the requirements of vblank swapping.
|
2008-09-30 13:14:26 -06:00
|
|
|
*/
|
2008-11-04 13:01:24 -07:00
|
|
|
return -EINVAL;
|
2006-10-24 07:37:43 -06:00
|
|
|
}
|
|
|
|
|
2010-10-27 07:44:35 -06:00
|
|
|
static u32
|
|
|
|
ring_last_seqno(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:56 -06:00
|
|
|
{
|
2010-10-27 07:44:35 -06:00
|
|
|
return list_entry(ring->request_list.prev,
|
|
|
|
struct drm_i915_gem_request, list)->seqno;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
|
|
|
|
{
|
|
|
|
if (list_empty(&ring->request_list) ||
|
|
|
|
i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
|
|
|
|
/* Issue a wake-up to catch stuck h/w. */
|
2010-10-27 08:27:33 -06:00
|
|
|
if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
|
2010-10-27 07:44:35 -06:00
|
|
|
DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
|
|
|
|
ring->name,
|
2010-10-27 08:27:33 -06:00
|
|
|
ring->waiting_seqno,
|
2010-10-27 07:44:35 -06:00
|
|
|
ring->get_seqno(ring));
|
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
*err = true;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
2009-09-14 15:48:44 -06:00
|
|
|
}
|
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
static bool kick_ring(struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = ring->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 tmp = I915_READ_CTL(ring);
|
|
|
|
if (tmp & RING_WAIT) {
|
|
|
|
DRM_ERROR("Kicking stuck wait on %s\n",
|
|
|
|
ring->name);
|
|
|
|
I915_WRITE_CTL(ring, tmp);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-09-14 15:48:44 -06:00
|
|
|
/**
|
|
|
|
* This is called when the chip hasn't reported back with completed
|
|
|
|
* batchbuffers in a long time. The first time this is called we simply record
|
|
|
|
* ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
|
|
|
|
* again, we assume the chip is wedged and try to fix it.
|
|
|
|
*/
|
|
|
|
void i915_hangcheck_elapsed(unsigned long data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *)data;
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2011-11-27 10:58:17 -07:00
|
|
|
uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
|
2010-10-27 07:44:35 -06:00
|
|
|
bool err = false;
|
|
|
|
|
2011-06-29 11:26:42 -06:00
|
|
|
if (!i915_enable_hangcheck)
|
|
|
|
return;
|
|
|
|
|
2010-10-27 07:44:35 -06:00
|
|
|
/* If all work is done then ACTHD clearly hasn't advanced. */
|
2010-12-04 04:30:53 -07:00
|
|
|
if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
|
|
|
|
i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
|
|
|
|
i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
|
2010-10-27 07:44:35 -06:00
|
|
|
dev_priv->hangcheck_count = 0;
|
|
|
|
if (err)
|
|
|
|
goto repeat;
|
|
|
|
return;
|
|
|
|
}
|
2010-01-08 15:25:16 -07:00
|
|
|
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
2010-06-06 05:16:24 -06:00
|
|
|
instdone = I915_READ(INSTDONE);
|
|
|
|
instdone1 = 0;
|
|
|
|
} else {
|
|
|
|
instdone = I915_READ(INSTDONE_I965);
|
|
|
|
instdone1 = I915_READ(INSTDONE1);
|
|
|
|
}
|
2011-11-27 10:58:17 -07:00
|
|
|
acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
|
|
|
|
acthd_bsd = HAS_BSD(dev) ?
|
|
|
|
intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
|
|
|
|
acthd_blt = HAS_BLT(dev) ?
|
|
|
|
intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
|
2009-09-14 15:48:44 -06:00
|
|
|
|
2010-06-06 05:16:24 -06:00
|
|
|
if (dev_priv->last_acthd == acthd &&
|
2011-11-27 10:58:17 -07:00
|
|
|
dev_priv->last_acthd_bsd == acthd_bsd &&
|
|
|
|
dev_priv->last_acthd_blt == acthd_blt &&
|
2010-06-06 05:16:24 -06:00
|
|
|
dev_priv->last_instdone == instdone &&
|
|
|
|
dev_priv->last_instdone1 == instdone1) {
|
|
|
|
if (dev_priv->hangcheck_count++ > 1) {
|
|
|
|
DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
|
2011-12-14 05:57:21 -07:00
|
|
|
i915_handle_error(dev, true);
|
2010-08-08 13:38:12 -06:00
|
|
|
|
|
|
|
if (!IS_GEN2(dev)) {
|
|
|
|
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
|
|
|
* If so we can simply poke the RB_WAIT bit
|
|
|
|
* and break the hang. This should work on
|
|
|
|
* all but the second generation chipsets.
|
|
|
|
*/
|
2010-12-04 04:30:53 -07:00
|
|
|
if (kick_ring(&dev_priv->ring[RCS]))
|
|
|
|
goto repeat;
|
|
|
|
|
|
|
|
if (HAS_BSD(dev) &&
|
|
|
|
kick_ring(&dev_priv->ring[VCS]))
|
|
|
|
goto repeat;
|
|
|
|
|
|
|
|
if (HAS_BLT(dev) &&
|
|
|
|
kick_ring(&dev_priv->ring[BCS]))
|
2010-10-27 07:44:35 -06:00
|
|
|
goto repeat;
|
2010-08-08 13:38:12 -06:00
|
|
|
}
|
|
|
|
|
2010-06-06 05:16:24 -06:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dev_priv->hangcheck_count = 0;
|
|
|
|
|
|
|
|
dev_priv->last_acthd = acthd;
|
2011-11-27 10:58:17 -07:00
|
|
|
dev_priv->last_acthd_bsd = acthd_bsd;
|
|
|
|
dev_priv->last_acthd_blt = acthd_blt;
|
2010-06-06 05:16:24 -06:00
|
|
|
dev_priv->last_instdone = instdone;
|
|
|
|
dev_priv->last_instdone1 = instdone1;
|
|
|
|
}
|
2009-09-14 15:48:44 -06:00
|
|
|
|
2010-10-27 07:44:35 -06:00
|
|
|
repeat:
|
2009-09-14 15:48:44 -06:00
|
|
|
/* Reset timer case chip hangs without another request being added */
|
2010-09-13 16:44:34 -06:00
|
|
|
mod_timer(&dev_priv->hangcheck_timer,
|
|
|
|
jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
|
2009-09-14 15:48:44 -06:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* drm_dma.h hooks
|
|
|
|
*/
|
2011-06-28 14:00:41 -06:00
|
|
|
static void ironlake_irq_preinstall(struct drm_device *dev)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
|
2011-04-07 14:53:55 -06:00
|
|
|
atomic_set(&dev_priv->irq_received, 0);
|
|
|
|
|
|
|
|
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
|
|
|
|
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
|
2011-05-18 14:51:43 -06:00
|
|
|
if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
|
|
|
|
INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
|
2011-04-07 14:53:55 -06:00
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
2011-07-01 12:08:56 -06:00
|
|
|
if (IS_GEN6(dev) || IS_GEN7(dev)) {
|
2011-06-17 12:32:19 -06:00
|
|
|
/* Workaround stalls observed on Sandy Bridge GPUs by
|
|
|
|
* making the blitter command streamer generate a
|
|
|
|
* write to the Hardware Status Page for
|
|
|
|
* MI_USER_INTERRUPT. This appears to serialize the
|
|
|
|
* previous seqno write out before the interrupt
|
|
|
|
* happens.
|
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
|
2011-06-21 11:37:59 -06:00
|
|
|
I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
|
2011-06-17 12:32:19 -06:00
|
|
|
}
|
2009-06-08 00:40:19 -06:00
|
|
|
|
|
|
|
/* XXX hotplug from PCH */
|
|
|
|
|
|
|
|
I915_WRITE(DEIMR, 0xffffffff);
|
|
|
|
I915_WRITE(DEIER, 0x0);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIER);
|
2009-06-08 00:40:19 -06:00
|
|
|
|
|
|
|
/* and GT */
|
|
|
|
I915_WRITE(GTIMR, 0xffffffff);
|
|
|
|
I915_WRITE(GTIER, 0x0);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(GTIER);
|
2009-11-03 11:57:21 -07:00
|
|
|
|
|
|
|
/* south display irq */
|
|
|
|
I915_WRITE(SDEIMR, 0xffffffff);
|
|
|
|
I915_WRITE(SDEIER, 0x0);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(SDEIER);
|
2009-06-08 00:40:19 -06:00
|
|
|
}
|
|
|
|
|
2011-09-19 14:31:02 -06:00
|
|
|
/*
|
|
|
|
* Enable digital hotplug on the PCH, and configure the DP short pulse
|
|
|
|
* duration to 2ms (which is the minimum in the Display Port spec)
|
|
|
|
*
|
|
|
|
* This register is the same on all known PCH chips.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void ironlake_enable_pch_hotplug(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
u32 hotplug;
|
|
|
|
|
|
|
|
hotplug = I915_READ(PCH_PORT_HOTPLUG);
|
|
|
|
hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
|
|
|
|
hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
|
|
|
|
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int ironlake_irq_postinstall(struct drm_device *dev)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
/* enable kind of interrupts always enabled */
|
2010-01-29 12:18:31 -07:00
|
|
|
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
|
|
|
|
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
|
2010-12-04 04:30:53 -07:00
|
|
|
u32 render_irqs;
|
2010-10-08 03:21:06 -06:00
|
|
|
u32 hotplug_mask;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2011-04-07 14:53:55 -06:00
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
|
|
|
|
if (HAS_BSD(dev))
|
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
|
|
|
|
if (HAS_BLT(dev))
|
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
|
|
|
|
|
|
|
|
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
2010-12-04 04:30:53 -07:00
|
|
|
dev_priv->irq_mask = ~display_mask;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
|
|
|
/* should always can generate irq */
|
|
|
|
I915_WRITE(DEIIR, I915_READ(DEIIR));
|
2010-12-04 04:30:53 -07:00
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(DEIER);
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
dev_priv->gt_irq_mask = ~0;
|
2009-06-08 00:40:19 -06:00
|
|
|
|
|
|
|
I915_WRITE(GTIIR, I915_READ(GTIIR));
|
2010-12-04 04:30:53 -07:00
|
|
|
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
2010-09-19 07:40:43 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
if (IS_GEN6(dev))
|
|
|
|
render_irqs =
|
|
|
|
GT_USER_INTERRUPT |
|
|
|
|
GT_GEN6_BSD_USER_INTERRUPT |
|
|
|
|
GT_BLT_USER_INTERRUPT;
|
|
|
|
else
|
|
|
|
render_irqs =
|
2010-12-05 08:08:31 -07:00
|
|
|
GT_USER_INTERRUPT |
|
2010-12-15 02:56:50 -07:00
|
|
|
GT_PIPE_NOTIFY |
|
2010-12-04 04:30:53 -07:00
|
|
|
GT_BSD_USER_INTERRUPT;
|
|
|
|
I915_WRITE(GTIER, render_irqs);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(GTIER);
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2010-10-08 03:21:06 -06:00
|
|
|
if (HAS_PCH_CPT(dev)) {
|
2011-02-16 02:36:05 -07:00
|
|
|
hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
|
|
|
|
SDE_PORTB_HOTPLUG_CPT |
|
|
|
|
SDE_PORTC_HOTPLUG_CPT |
|
|
|
|
SDE_PORTD_HOTPLUG_CPT);
|
2010-10-08 03:21:06 -06:00
|
|
|
} else {
|
2011-02-16 02:36:05 -07:00
|
|
|
hotplug_mask = (SDE_CRT_HOTPLUG |
|
|
|
|
SDE_PORTB_HOTPLUG |
|
|
|
|
SDE_PORTC_HOTPLUG |
|
|
|
|
SDE_PORTD_HOTPLUG |
|
|
|
|
SDE_AUX_MASK);
|
2010-10-08 03:21:06 -06:00
|
|
|
}
|
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
dev_priv->pch_irq_mask = ~hotplug_mask;
|
2009-11-03 11:57:21 -07:00
|
|
|
|
|
|
|
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
|
2010-12-04 04:30:53 -07:00
|
|
|
I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
|
|
|
|
I915_WRITE(SDEIER, hotplug_mask);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(SDEIER);
|
2009-11-03 11:57:21 -07:00
|
|
|
|
2011-09-19 14:31:02 -06:00
|
|
|
ironlake_enable_pch_hotplug(dev);
|
|
|
|
|
2010-01-29 12:27:07 -07:00
|
|
|
if (IS_IRONLAKE_M(dev)) {
|
|
|
|
/* Clear & enable PCU event interrupts */
|
|
|
|
I915_WRITE(DEIIR, DE_PCU_EVENT);
|
|
|
|
I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
|
|
|
|
ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
|
|
|
|
}
|
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static int ivybridge_irq_postinstall(struct drm_device *dev)
|
2011-04-06 13:13:38 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
/* enable kind of interrupts always enabled */
|
|
|
|
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
|
|
|
|
DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
|
|
|
|
DE_PLANEB_FLIP_DONE_IVB;
|
|
|
|
u32 render_irqs;
|
|
|
|
u32 hotplug_mask;
|
|
|
|
|
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
|
|
|
|
if (HAS_BSD(dev))
|
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
|
|
|
|
if (HAS_BLT(dev))
|
|
|
|
DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
|
|
|
|
|
|
|
|
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
|
|
|
dev_priv->irq_mask = ~display_mask;
|
|
|
|
|
|
|
|
/* should always can generate irq */
|
|
|
|
I915_WRITE(DEIIR, I915_READ(DEIIR));
|
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
|
|
|
|
DE_PIPEB_VBLANK_IVB);
|
|
|
|
POSTING_READ(DEIER);
|
|
|
|
|
|
|
|
dev_priv->gt_irq_mask = ~0;
|
|
|
|
|
|
|
|
I915_WRITE(GTIIR, I915_READ(GTIIR));
|
|
|
|
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
|
|
|
|
|
|
|
render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
|
|
|
|
GT_BLT_USER_INTERRUPT;
|
|
|
|
I915_WRITE(GTIER, render_irqs);
|
|
|
|
POSTING_READ(GTIER);
|
|
|
|
|
|
|
|
hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
|
|
|
|
SDE_PORTB_HOTPLUG_CPT |
|
|
|
|
SDE_PORTC_HOTPLUG_CPT |
|
|
|
|
SDE_PORTD_HOTPLUG_CPT);
|
|
|
|
dev_priv->pch_irq_mask = ~hotplug_mask;
|
|
|
|
|
|
|
|
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
|
|
|
|
I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
|
|
|
|
I915_WRITE(SDEIER, hotplug_mask);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
|
2011-09-19 14:31:02 -06:00
|
|
|
ironlake_enable_pch_hotplug(dev);
|
|
|
|
|
2011-04-06 13:13:38 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static void i915_driver_irq_preinstall(struct drm_device * dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2011-02-07 13:26:52 -07:00
|
|
|
int pipe;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
atomic_set(&dev_priv->irq_received, 0);
|
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
|
2009-07-11 14:48:03 -06:00
|
|
|
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
|
2009-06-08 00:40:19 -06:00
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2008-09-30 13:14:26 -06:00
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
2008-07-29 13:10:39 -06:00
|
|
|
I915_WRITE(IER, 0x0);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(IER);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2009-12-11 12:07:17 -07:00
|
|
|
/*
|
|
|
|
* Must be called after intel_modeset_init or hotplug interrupts won't be
|
|
|
|
* enabled correctly.
|
|
|
|
*/
|
2011-06-28 14:00:41 -06:00
|
|
|
static int i915_driver_irq_postinstall(struct drm_device *dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2009-03-31 15:11:15 -06:00
|
|
|
u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
|
2009-06-18 17:56:52 -06:00
|
|
|
u32 error_mask;
|
2008-09-30 13:14:26 -06:00
|
|
|
|
|
|
|
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
|
|
|
|
2008-11-04 03:03:27 -07:00
|
|
|
/* Unmask the interrupts that we always want on. */
|
2010-12-04 04:30:53 -07:00
|
|
|
dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
|
2008-11-04 03:03:27 -07:00
|
|
|
|
|
|
|
dev_priv->pipestat[0] = 0;
|
|
|
|
dev_priv->pipestat[1] = 0;
|
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
/* Enable in IER... */
|
|
|
|
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
|
|
|
|
/* and unmask in IMR */
|
2010-12-04 04:30:53 -07:00
|
|
|
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
|
2009-03-31 15:11:15 -06:00
|
|
|
}
|
|
|
|
|
2009-06-18 17:56:52 -06:00
|
|
|
/*
|
|
|
|
* Enable some error detection, note the instruction error mask
|
|
|
|
* bit is reserved, so we leave it masked.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
error_mask = ~(GM45_ERROR_PAGE_TABLE |
|
|
|
|
GM45_ERROR_MEM_PRIV |
|
|
|
|
GM45_ERROR_CP_PRIV |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
} else {
|
|
|
|
error_mask = ~(I915_ERROR_PAGE_TABLE |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
}
|
|
|
|
I915_WRITE(EMR, error_mask);
|
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
2010-05-27 15:26:45 -06:00
|
|
|
I915_WRITE(IER, enable_mask);
|
2010-11-16 08:55:10 -07:00
|
|
|
POSTING_READ(IER);
|
2008-07-29 13:10:39 -06:00
|
|
|
|
2010-05-27 15:26:45 -06:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
|
|
|
/* Note HDMI and DP share bits */
|
|
|
|
if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
|
|
|
|
hotplug_en |= HDMIB_HOTPLUG_INT_EN;
|
|
|
|
if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
|
|
|
|
hotplug_en |= HDMIC_HOTPLUG_INT_EN;
|
|
|
|
if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
|
|
|
|
hotplug_en |= HDMID_HOTPLUG_INT_EN;
|
|
|
|
if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
|
|
|
|
hotplug_en |= SDVOC_HOTPLUG_INT_EN;
|
|
|
|
if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
|
|
|
|
hotplug_en |= SDVOB_HOTPLUG_INT_EN;
|
2010-06-12 03:21:18 -06:00
|
|
|
if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
|
2010-05-27 15:26:45 -06:00
|
|
|
hotplug_en |= CRT_HOTPLUG_INT_EN;
|
2010-06-12 03:21:18 -06:00
|
|
|
|
|
|
|
/* Programming the CRT detection parameters tends
|
|
|
|
to generate a spurious hotplug event about three
|
|
|
|
seconds later. So just do it once.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
|
|
|
|
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
|
|
|
|
}
|
|
|
|
|
2010-05-27 15:26:45 -06:00
|
|
|
/* Ignore TV since it's buggy */
|
|
|
|
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
|
|
|
|
}
|
|
|
|
|
2010-08-24 02:02:58 -06:00
|
|
|
intel_opregion_enable_asle(dev);
|
2008-09-30 13:14:26 -06:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static void ironlake_irq_uninstall(struct drm_device *dev)
|
2009-06-08 00:40:19 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2011-04-07 14:53:55 -06:00
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_priv->vblank_pipe = 0;
|
|
|
|
|
2009-06-08 00:40:19 -06:00
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
|
|
|
|
|
|
|
I915_WRITE(DEIMR, 0xffffffff);
|
|
|
|
I915_WRITE(DEIER, 0x0);
|
|
|
|
I915_WRITE(DEIIR, I915_READ(DEIIR));
|
|
|
|
|
|
|
|
I915_WRITE(GTIMR, 0xffffffff);
|
|
|
|
I915_WRITE(GTIER, 0x0);
|
|
|
|
I915_WRITE(GTIIR, I915_READ(GTIIR));
|
2011-09-20 11:12:44 -06:00
|
|
|
|
|
|
|
I915_WRITE(SDEIMR, 0xffffffff);
|
|
|
|
I915_WRITE(SDEIER, 0x0);
|
|
|
|
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
|
2009-06-08 00:40:19 -06:00
|
|
|
}
|
|
|
|
|
2011-06-28 14:00:41 -06:00
|
|
|
static void i915_driver_irq_uninstall(struct drm_device * dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
2011-02-07 13:26:52 -07:00
|
|
|
int pipe;
|
2006-02-17 21:17:04 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
dev_priv->vblank_pipe = 0;
|
|
|
|
|
2009-03-31 15:11:15 -06:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2008-09-30 13:14:26 -06:00
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2008-09-30 13:14:26 -06:00
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
2008-07-29 13:10:39 -06:00
|
|
|
I915_WRITE(IER, 0x0);
|
2008-05-06 20:15:39 -06:00
|
|
|
|
2011-02-07 13:26:52 -07:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
|
2008-11-04 03:03:27 -07:00
|
|
|
I915_WRITE(IIR, I915_READ(IIR));
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2011-06-28 14:00:41 -06:00
|
|
|
|
|
|
|
void intel_irq_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
|
|
|
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
|
|
|
if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
|
|
|
|
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
|
|
|
|
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
|
|
|
|
}
|
|
|
|
|
2011-08-12 18:05:54 -06:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
|
|
|
|
else
|
|
|
|
dev->driver->get_vblank_timestamp = NULL;
|
2011-06-28 14:00:41 -06:00
|
|
|
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
|
|
|
|
|
|
|
|
if (IS_IVYBRIDGE(dev)) {
|
|
|
|
/* Share pre & uninstall handlers with ILK/SNB */
|
|
|
|
dev->driver->irq_handler = ivybridge_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = ironlake_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = ironlake_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = ivybridge_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = ivybridge_disable_vblank;
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
dev->driver->irq_handler = ironlake_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = ironlake_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = ironlake_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = ironlake_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = ironlake_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = ironlake_disable_vblank;
|
|
|
|
} else {
|
|
|
|
dev->driver->irq_preinstall = i915_driver_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i915_driver_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = i915_driver_irq_uninstall;
|
|
|
|
dev->driver->irq_handler = i915_driver_irq_handler;
|
|
|
|
dev->driver->enable_vblank = i915_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = i915_disable_vblank;
|
|
|
|
}
|
|
|
|
}
|