2012-02-01 14:04:47 -07:00
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/*
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* Driver for the NVIDIA Tegra pinmux
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*
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* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
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*
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* Derived from code:
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2010 NVIDIA Corporation
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* Copyright (C) 2009-2011 ST-Ericsson AB
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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2012-04-04 09:27:50 -06:00
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#include <linux/pinctrl/machine.h>
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2012-02-01 14:04:47 -07:00
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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2012-04-04 09:27:50 -06:00
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#include <linux/slab.h>
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2012-02-01 14:04:47 -07:00
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#include <mach/pinconf-tegra.h>
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#include "pinctrl-tegra.h"
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ARM: tegra: Switch to new pinctrl driver
* Rename old pinmux and new pinctrl platform driver and DT match table
entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
in pinctrl format.
Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.
All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.
Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.
Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2011-12-13 15:21:01 -07:00
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#define DRIVER_NAME "tegra-pinmux"
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2012-02-01 14:04:47 -07:00
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struct tegra_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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const struct tegra_pinctrl_soc_data *soc;
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int nbanks;
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void __iomem **regs;
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};
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
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{
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return readl(pmx->regs[bank] + reg);
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}
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static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
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{
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writel(val, pmx->regs[bank] + reg);
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}
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2012-03-29 23:55:40 -06:00
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static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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2012-02-01 14:04:47 -07:00
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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2012-03-29 23:55:40 -06:00
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return pmx->soc->ngroups;
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2012-02-01 14:04:47 -07:00
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}
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static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->groups[group].name;
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}
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static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->soc->groups[group].pins;
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*num_pins = pmx->soc->groups[group].npins;
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return 0;
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}
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static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, " " DRIVER_NAME);
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}
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2012-04-04 09:27:50 -06:00
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static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
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unsigned *num_maps, unsigned reserve)
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{
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unsigned old_num = *reserved_maps;
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unsigned new_num = *num_maps + reserve;
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struct pinctrl_map *new_map;
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if (old_num >= new_num)
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return 0;
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new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
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if (!new_map)
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return -ENOMEM;
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memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
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*map = new_map;
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*reserved_maps = new_num;
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return 0;
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}
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static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
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unsigned *num_maps, const char *group,
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const char *function)
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{
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if (*num_maps == *reserved_maps)
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return -ENOSPC;
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(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[*num_maps].data.mux.group = group;
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(*map)[*num_maps].data.mux.function = function;
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(*num_maps)++;
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return 0;
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}
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static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
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unsigned *num_maps, const char *group,
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unsigned long *configs, unsigned num_configs)
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{
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unsigned long *dup_configs;
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if (*num_maps == *reserved_maps)
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return -ENOSPC;
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dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
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GFP_KERNEL);
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if (!dup_configs)
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return -ENOMEM;
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(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
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(*map)[*num_maps].data.configs.group_or_pin = group;
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(*map)[*num_maps].data.configs.configs = dup_configs;
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(*map)[*num_maps].data.configs.num_configs = num_configs;
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(*num_maps)++;
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return 0;
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}
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static int add_config(unsigned long **configs, unsigned *num_configs,
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unsigned long config)
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{
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unsigned old_num = *num_configs;
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unsigned new_num = old_num + 1;
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unsigned long *new_configs;
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new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
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GFP_KERNEL);
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if (!new_configs)
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return -ENOMEM;
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new_configs[old_num] = config;
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*configs = new_configs;
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*num_configs = new_num;
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return 0;
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}
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void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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int i;
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for (i = 0; i < num_maps; i++)
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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kfree(map[i].data.configs.configs);
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kfree(map);
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}
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static const struct cfg_param {
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const char *property;
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enum tegra_pinconf_param param;
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} cfg_params[] = {
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{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
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{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
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{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
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{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
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{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
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{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
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{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
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{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
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{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
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{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
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{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
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{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
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{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
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};
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int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
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struct pinctrl_map **map,
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unsigned *reserved_maps,
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unsigned *num_maps)
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{
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int ret, i;
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const char *function;
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u32 val;
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unsigned long config;
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unsigned long *configs = NULL;
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unsigned num_configs = 0;
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unsigned reserve;
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struct property *prop;
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const char *group;
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ret = of_property_read_string(np, "nvidia,function", &function);
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if (ret < 0)
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function = NULL;
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for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
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ret = of_property_read_u32(np, cfg_params[i].property, &val);
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if (!ret) {
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config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
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ret = add_config(&configs, &num_configs, config);
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if (ret < 0)
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goto exit;
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}
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}
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reserve = 0;
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if (function != NULL)
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reserve++;
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if (num_configs)
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reserve++;
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ret = of_property_count_strings(np, "nvidia,pins");
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if (ret < 0)
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goto exit;
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reserve *= ret;
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ret = reserve_map(map, reserved_maps, num_maps, reserve);
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if (ret < 0)
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goto exit;
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of_property_for_each_string(np, "nvidia,pins", prop, group) {
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if (function) {
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ret = add_map_mux(map, reserved_maps, num_maps,
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group, function);
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if (ret < 0)
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goto exit;
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}
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if (num_configs) {
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ret = add_map_configs(map, reserved_maps, num_maps,
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group, configs, num_configs);
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if (ret < 0)
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goto exit;
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}
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}
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ret = 0;
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exit:
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kfree(configs);
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return ret;
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}
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int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, unsigned *num_maps)
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{
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unsigned reserved_maps;
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struct device_node *np;
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int ret;
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reserved_maps = 0;
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*map = NULL;
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*num_maps = 0;
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for_each_child_of_node(np_config, np) {
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ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
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num_maps);
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if (ret < 0) {
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tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
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return ret;
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}
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}
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return 0;
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}
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|
2012-02-01 14:04:47 -07:00
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static struct pinctrl_ops tegra_pinctrl_ops = {
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2012-03-29 23:55:40 -06:00
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.get_groups_count = tegra_pinctrl_get_groups_count,
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2012-02-01 14:04:47 -07:00
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.get_group_name = tegra_pinctrl_get_group_name,
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.get_group_pins = tegra_pinctrl_get_group_pins,
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.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
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2012-04-04 09:27:50 -06:00
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.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
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.dt_free_map = tegra_pinctrl_dt_free_map,
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2012-02-01 14:04:47 -07:00
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};
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2012-03-29 23:55:40 -06:00
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static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
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2012-02-01 14:04:47 -07:00
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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2012-03-29 23:55:40 -06:00
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return pmx->soc->nfunctions;
|
2012-02-01 14:04:47 -07:00
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}
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static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->functions[function].name;
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}
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static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->soc->functions[function].groups;
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*num_groups = pmx->soc->functions[function].ngroups;
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return 0;
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}
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|
|
static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
|
|
|
|
unsigned group)
|
|
|
|
{
|
|
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
const struct tegra_pingroup *g;
|
|
|
|
int i;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
|
|
|
|
if (g->mux_reg < 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
|
|
|
|
if (g->funcs[i] == function)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(g->funcs))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
|
|
|
val &= ~(0x3 << g->mux_bit);
|
|
|
|
val |= i << g->mux_bit;
|
|
|
|
pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned function, unsigned group)
|
|
|
|
{
|
|
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
const struct tegra_pingroup *g;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
|
|
|
|
if (g->mux_reg < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
|
|
|
val &= ~(0x3 << g->mux_bit);
|
|
|
|
val |= g->func_safe << g->mux_bit;
|
|
|
|
pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pinmux_ops tegra_pinmux_ops = {
|
2012-03-29 23:55:40 -06:00
|
|
|
.get_functions_count = tegra_pinctrl_get_funcs_count,
|
2012-02-01 14:04:47 -07:00
|
|
|
.get_function_name = tegra_pinctrl_get_func_name,
|
|
|
|
.get_function_groups = tegra_pinctrl_get_func_groups,
|
|
|
|
.enable = tegra_pinctrl_enable,
|
|
|
|
.disable = tegra_pinctrl_disable,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
|
|
|
const struct tegra_pingroup *g,
|
|
|
|
enum tegra_pinconf_param param,
|
|
|
|
s8 *bank, s16 *reg, s8 *bit, s8 *width)
|
|
|
|
{
|
|
|
|
switch (param) {
|
|
|
|
case TEGRA_PINCONF_PARAM_PULL:
|
|
|
|
*bank = g->pupd_bank;
|
|
|
|
*reg = g->pupd_reg;
|
|
|
|
*bit = g->pupd_bit;
|
|
|
|
*width = 2;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_TRISTATE:
|
|
|
|
*bank = g->tri_bank;
|
|
|
|
*reg = g->tri_reg;
|
|
|
|
*bit = g->tri_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
|
|
|
|
*bank = g->einput_bank;
|
|
|
|
*reg = g->einput_reg;
|
|
|
|
*bit = g->einput_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
|
|
|
|
*bank = g->odrain_bank;
|
|
|
|
*reg = g->odrain_reg;
|
|
|
|
*bit = g->odrain_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_LOCK:
|
|
|
|
*bank = g->lock_bank;
|
|
|
|
*reg = g->lock_reg;
|
|
|
|
*bit = g->lock_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_IORESET:
|
|
|
|
*bank = g->ioreset_bank;
|
|
|
|
*reg = g->ioreset_reg;
|
|
|
|
*bit = g->ioreset_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->hsm_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_SCHMITT:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->schmitt_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->lpmd_bit;
|
|
|
|
*width = 1;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->drvdn_bit;
|
|
|
|
*width = g->drvdn_width;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->drvup_bit;
|
|
|
|
*width = g->drvup_width;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->slwf_bit;
|
|
|
|
*width = g->slwf_width;
|
|
|
|
break;
|
|
|
|
case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
|
|
|
|
*bank = g->drv_bank;
|
|
|
|
*reg = g->drv_reg;
|
|
|
|
*bit = g->slwr_bit;
|
|
|
|
*width = g->slwr_width;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(pmx->dev, "Invalid config param %04x\n", param);
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (*reg < 0) {
|
|
|
|
dev_err(pmx->dev,
|
|
|
|
"Config param %04x not supported on group %s\n",
|
|
|
|
param, g->name);
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned pin, unsigned long *config)
|
|
|
|
{
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned pin, unsigned long config)
|
|
|
|
{
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned group, unsigned long *config)
|
|
|
|
{
|
|
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
|
|
|
|
u16 arg;
|
|
|
|
const struct tegra_pingroup *g;
|
|
|
|
int ret;
|
|
|
|
s8 bank, bit, width;
|
|
|
|
s16 reg;
|
|
|
|
u32 val, mask;
|
|
|
|
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
|
|
|
|
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
val = pmx_readl(pmx, bank, reg);
|
|
|
|
mask = (1 << width) - 1;
|
|
|
|
arg = (val >> bit) & mask;
|
|
|
|
|
|
|
|
*config = TEGRA_PINCONF_PACK(param, arg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned group, unsigned long config)
|
|
|
|
{
|
|
|
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
|
|
|
|
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
|
|
|
|
const struct tegra_pingroup *g;
|
|
|
|
int ret;
|
|
|
|
s8 bank, bit, width;
|
|
|
|
s16 reg;
|
|
|
|
u32 val, mask;
|
|
|
|
|
|
|
|
g = &pmx->soc->groups[group];
|
|
|
|
|
|
|
|
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
val = pmx_readl(pmx, bank, reg);
|
|
|
|
|
|
|
|
/* LOCK can't be cleared */
|
|
|
|
if (param == TEGRA_PINCONF_PARAM_LOCK) {
|
|
|
|
if ((val & BIT(bit)) && !arg)
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Special-case Boolean values; allow any non-zero as true */
|
|
|
|
if (width == 1)
|
|
|
|
arg = !!arg;
|
|
|
|
|
|
|
|
/* Range-check user-supplied value */
|
|
|
|
mask = (1 << width) - 1;
|
|
|
|
if (arg & ~mask)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Update register */
|
|
|
|
val &= ~(mask << bit);
|
|
|
|
val |= arg << bit;
|
|
|
|
pmx_writel(pmx, val, bank, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
|
|
|
struct seq_file *s, unsigned offset)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
|
|
|
struct seq_file *s, unsigned selector)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
struct pinconf_ops tegra_pinconf_ops = {
|
|
|
|
.pin_config_get = tegra_pinconf_get,
|
|
|
|
.pin_config_set = tegra_pinconf_set,
|
|
|
|
.pin_config_group_get = tegra_pinconf_group_get,
|
|
|
|
.pin_config_group_set = tegra_pinconf_group_set,
|
|
|
|
.pin_config_dbg_show = tegra_pinconf_dbg_show,
|
|
|
|
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
|
|
|
.name = "Tegra GPIOs",
|
|
|
|
.id = 0,
|
|
|
|
.base = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pinctrl_desc tegra_pinctrl_desc = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.pctlops = &tegra_pinctrl_ops,
|
|
|
|
.pmxops = &tegra_pinmux_ops,
|
|
|
|
.confops = &tegra_pinconf_ops,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
|
|
|
|
#ifdef CONFIG_PINCTRL_TEGRA20
|
|
|
|
{
|
ARM: tegra: Switch to new pinctrl driver
* Rename old pinmux and new pinctrl platform driver and DT match table
entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
in pinctrl format.
Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.
All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.
Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.
Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2011-12-13 15:21:01 -07:00
|
|
|
.compatible = "nvidia,tegra20-pinmux",
|
2012-02-01 14:04:47 -07:00
|
|
|
.data = tegra20_pinctrl_init,
|
|
|
|
},
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_PINCTRL_TEGRA30
|
|
|
|
{
|
ARM: tegra: Switch to new pinctrl driver
* Rename old pinmux and new pinctrl platform driver and DT match table
entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
in pinctrl format.
Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.
All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.
Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.
Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
2011-12-13 15:21:01 -07:00
|
|
|
.compatible = "nvidia,tegra30-pinmux",
|
2012-02-01 14:04:47 -07:00
|
|
|
.data = tegra30_pinctrl_init,
|
|
|
|
},
|
|
|
|
#endif
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
const struct of_device_id *match;
|
|
|
|
tegra_pinctrl_soc_initf initf = NULL;
|
|
|
|
struct tegra_pmx *pmx;
|
|
|
|
struct resource *res;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
|
|
|
|
if (match)
|
|
|
|
initf = (tegra_pinctrl_soc_initf)match->data;
|
|
|
|
#ifdef CONFIG_PINCTRL_TEGRA20
|
|
|
|
if (!initf)
|
|
|
|
initf = tegra20_pinctrl_init;
|
|
|
|
#endif
|
|
|
|
if (!initf) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Could not determine SoC-specific init func\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
|
|
|
|
if (!pmx) {
|
|
|
|
dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
pmx->dev = &pdev->dev;
|
|
|
|
|
|
|
|
(*initf)(&pmx->soc);
|
|
|
|
|
|
|
|
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
|
|
|
|
tegra_pinctrl_desc.pins = pmx->soc->pins;
|
|
|
|
tegra_pinctrl_desc.npins = pmx->soc->npins;
|
|
|
|
|
|
|
|
for (i = 0; ; i++) {
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
|
|
if (!res)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
pmx->nbanks = i;
|
|
|
|
|
|
|
|
pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!pmx->regs) {
|
|
|
|
dev_err(&pdev->dev, "Can't alloc regs pointer\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < pmx->nbanks; i++) {
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(&pdev->dev, "Missing MEM resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!devm_request_mem_region(&pdev->dev, res->start,
|
|
|
|
resource_size(res),
|
|
|
|
dev_name(&pdev->dev))) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Couldn't request MEM resource %d\n", i);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
|
|
|
|
resource_size(res));
|
|
|
|
if (!pmx->regs[i]) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
|
|
|
|
if (IS_ERR(pmx->pctl)) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
|
|
|
return PTR_ERR(pmx->pctl);
|
|
|
|
}
|
|
|
|
|
|
|
|
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, pmx);
|
|
|
|
|
|
|
|
dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
pinctrl_remove_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
|
|
|
|
pinctrl_unregister(pmx->pctl);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver tegra_pinctrl_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = tegra_pinctrl_of_match,
|
|
|
|
},
|
|
|
|
.probe = tegra_pinctrl_probe,
|
|
|
|
.remove = __devexit_p(tegra_pinctrl_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init tegra_pinctrl_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&tegra_pinctrl_driver);
|
|
|
|
}
|
|
|
|
arch_initcall(tegra_pinctrl_init);
|
|
|
|
|
|
|
|
static void __exit tegra_pinctrl_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&tegra_pinctrl_driver);
|
|
|
|
}
|
|
|
|
module_exit(tegra_pinctrl_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
|