Merge branch 'msm-fixes-4.9' of git://people.freedesktop.org/~robclark/linux into drm-fixes
Fixes for some msm issues * 'msm-fixes-4.9' of git://people.freedesktop.org/~robclark/linux: drm/msm: Fix error handling crashes seen when VRAM allocation fails drm/msm/mdp5: 8x16 actually has 8 mixer stages drm/msm/mdp5: no scaling support on RGBn pipes for 8x16 drm/msm/mdp5: handle non-fullscreen base plane case drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks drm/msm/dsi: Queue HPD helper work in attach/detach callbacks
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commit
020a0bbc0d
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@ -139,6 +139,7 @@ struct msm_dsi_host {
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u32 err_work_state;
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struct work_struct err_work;
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struct work_struct hpd_work;
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struct workqueue_struct *workqueue;
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/* DSI 6G TX buffer*/
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@ -1294,6 +1295,14 @@ static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
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wmb(); /* make sure dsi controller enabled again */
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}
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static void dsi_hpd_worker(struct work_struct *work)
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{
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struct msm_dsi_host *msm_host =
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container_of(work, struct msm_dsi_host, hpd_work);
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drm_helper_hpd_irq_event(msm_host->dev);
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}
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static void dsi_err_worker(struct work_struct *work)
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{
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struct msm_dsi_host *msm_host =
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@ -1480,7 +1489,7 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
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DBG("id=%d", msm_host->id);
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if (msm_host->dev)
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drm_helper_hpd_irq_event(msm_host->dev);
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queue_work(msm_host->workqueue, &msm_host->hpd_work);
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return 0;
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}
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@ -1494,7 +1503,7 @@ static int dsi_host_detach(struct mipi_dsi_host *host,
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DBG("id=%d", msm_host->id);
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if (msm_host->dev)
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drm_helper_hpd_irq_event(msm_host->dev);
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queue_work(msm_host->workqueue, &msm_host->hpd_work);
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return 0;
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}
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@ -1748,6 +1757,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
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/* setup workqueue */
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msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
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INIT_WORK(&msm_host->err_work, dsi_err_worker);
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INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
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msm_dsi->host = &msm_host->base;
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msm_dsi->id = msm_host->id;
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@ -521,6 +521,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.name = vco_name,
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.flags = CLK_IGNORE_UNUSED,
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.ops = &clk_ops_dsi_pll_28nm_vco,
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};
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struct device *dev = &pll_28nm->pdev->dev;
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@ -412,6 +412,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
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struct clk_init_data vco_init = {
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.parent_names = (const char *[]){ "pxo" },
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.num_parents = 1,
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.flags = CLK_IGNORE_UNUSED,
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.ops = &clk_ops_dsi_pll_28nm_vco,
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};
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struct device *dev = &pll_28nm->pdev->dev;
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@ -702,6 +702,7 @@ static struct clk_init_data pll_init = {
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.ops = &hdmi_8996_pll_ops,
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.parent_names = hdmi_pll_parents,
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.num_parents = ARRAY_SIZE(hdmi_pll_parents),
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.flags = CLK_IGNORE_UNUSED,
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};
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int msm_hdmi_pll_8996_init(struct platform_device *pdev)
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@ -424,6 +424,7 @@ static struct clk_init_data pll_init = {
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.ops = &hdmi_pll_ops,
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.parent_names = hdmi_pll_parents,
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.num_parents = ARRAY_SIZE(hdmi_pll_parents),
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.flags = CLK_IGNORE_UNUSED,
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};
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int msm_hdmi_pll_8960_init(struct platform_device *pdev)
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@ -272,7 +272,7 @@ const struct mdp5_cfg_hw msm8x16_config = {
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.count = 2,
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.base = { 0x14000, 0x16000 },
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.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
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MDP_PIPE_CAP_DECIMATION,
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},
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.pipe_dma = {
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.count = 1,
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@ -282,7 +282,7 @@ const struct mdp5_cfg_hw msm8x16_config = {
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.lm = {
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.count = 2, /* LM0 and LM3 */
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.base = { 0x44000, 0x47000 },
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.nb_stages = 5,
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.nb_stages = 8,
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.max_width = 2048,
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.max_height = 0xFFFF,
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},
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@ -223,12 +223,7 @@ static void blend_setup(struct drm_crtc *crtc)
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plane_cnt++;
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}
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/*
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* If there is no base layer, enable border color.
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* Although it's not possbile in current blend logic,
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* put it here as a reminder.
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*/
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if (!pstates[STAGE_BASE] && plane_cnt) {
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if (!pstates[STAGE_BASE]) {
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ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
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DBG("Border Color is enabled");
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}
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@ -365,6 +360,15 @@ static int pstate_cmp(const void *a, const void *b)
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return pa->state->zpos - pb->state->zpos;
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}
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/* is there a helper for this? */
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static bool is_fullscreen(struct drm_crtc_state *cstate,
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struct drm_plane_state *pstate)
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{
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return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
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((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
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((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
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}
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static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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@ -375,21 +379,11 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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struct plane_state pstates[STAGE_MAX + 1];
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const struct mdp5_cfg_hw *hw_cfg;
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const struct drm_plane_state *pstate;
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int cnt = 0, i;
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int cnt = 0, base = 0, i;
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DBG("%s: check", mdp5_crtc->name);
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/* verify that there are not too many planes attached to crtc
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* and that we don't have conflicting mixer stages:
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*/
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hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
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drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
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if (cnt >= (hw_cfg->lm.nb_stages)) {
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dev_err(dev->dev, "too many planes!\n");
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return -EINVAL;
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}
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pstates[cnt].plane = plane;
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pstates[cnt].state = to_mdp5_plane_state(pstate);
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@ -399,8 +393,24 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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/* assign a stage based on sorted zpos property */
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sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
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/* if the bottom-most layer is not fullscreen, we need to use
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* it for solid-color:
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*/
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if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base))
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base++;
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/* verify that there are not too many planes attached to crtc
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* and that we don't have conflicting mixer stages:
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*/
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hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
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if ((cnt + base) >= hw_cfg->lm.nb_stages) {
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dev_err(dev->dev, "too many planes!\n");
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return -EINVAL;
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}
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for (i = 0; i < cnt; i++) {
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pstates[i].state->stage = STAGE_BASE + i;
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pstates[i].state->stage = STAGE_BASE + i + base;
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DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
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pipe2name(mdp5_plane_pipe(pstates[i].plane)),
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pstates[i].state->stage);
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@ -292,8 +292,7 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane,
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format = to_mdp_format(msm_framebuffer_format(state->fb));
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if (MDP_FORMAT_IS_YUV(format) &&
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!pipe_supports_yuv(mdp5_plane->caps)) {
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dev_err(plane->dev->dev,
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"Pipe doesn't support YUV\n");
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DBG("Pipe doesn't support YUV\n");
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return -EINVAL;
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}
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@ -301,8 +300,7 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane,
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if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) &&
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(((state->src_w >> 16) != state->crtc_w) ||
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((state->src_h >> 16) != state->crtc_h))) {
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dev_err(plane->dev->dev,
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"Pipe doesn't support scaling (%dx%d -> %dx%d)\n",
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DBG("Pipe doesn't support scaling (%dx%d -> %dx%d)\n",
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state->src_w >> 16, state->src_h >> 16,
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state->crtc_w, state->crtc_h);
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@ -313,8 +311,7 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane,
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vflip = !!(state->rotation & DRM_REFLECT_Y);
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if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) ||
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(hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) {
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dev_err(plane->dev->dev,
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"Pipe doesn't support flip\n");
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DBG("Pipe doesn't support flip\n");
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return -EINVAL;
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}
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@ -228,7 +228,7 @@ static int msm_drm_uninit(struct device *dev)
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flush_workqueue(priv->atomic_wq);
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destroy_workqueue(priv->atomic_wq);
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if (kms)
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if (kms && kms->funcs)
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kms->funcs->destroy(kms);
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if (gpu) {
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@ -163,6 +163,9 @@ void msm_gem_shrinker_init(struct drm_device *dev)
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void msm_gem_shrinker_cleanup(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier));
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unregister_shrinker(&priv->shrinker);
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if (priv->shrinker.nr_deferred) {
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WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier));
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unregister_shrinker(&priv->shrinker);
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}
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}
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