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arm: dts: add gpmi-nand support for imx7d sabresd 

add gpmi-nand support for imx7d sabresd

Signed-off-by: Han Xu <han.xu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Han Xu 2019-08-14 19:29:11 -05:00 committed by Dong Aisheng
parent 9a829f97bc
commit 0ca9c7cd87
4 changed files with 61 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
View File

@ -606,6 +606,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-gpmi-weim.dtb \
imx7d-sdb-m4.dtb \
imx7d-sdb-qspi.dtb \
imx7d-sdb-reva.dtb \

9
arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dts 100644
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@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-gpmi-weim.dtsi"

23
arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi 100644
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@ -0,0 +1,23 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&gpmi{
status = "okay";
};
/* &sai1{ */
/* status = "disabled"; */
/* }; */
&usdhc3{
status = "disabled";
};
&uart5{
status = "disabled";
};

28
arch/arm/boot/dts/imx7d-sdb.dts
View File

@ -264,6 +264,13 @@
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled";
nand-on-flash-bbt;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@ -608,6 +615,27 @@
>;
};
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */