drm/i915: Uncouple render/power ctx before suspending
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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9b3826bf84
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@ -820,6 +820,8 @@ int i915_save_state(struct drm_device *dev)
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if (HAS_PCH_SPLIT(dev))
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ironlake_disable_drps(dev);
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intel_disable_clock_gating(dev);
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/* Cache mode state */
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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@ -863,7 +865,7 @@ int i915_restore_state(struct drm_device *dev)
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}
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/* Clock gating state */
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intel_init_clock_gating(dev);
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intel_enable_clock_gating(dev);
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if (HAS_PCH_SPLIT(dev)) {
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ironlake_enable_drps(dev);
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@ -5828,7 +5828,7 @@ void intel_init_emon(struct drm_device *dev)
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dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
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}
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void intel_init_clock_gating(struct drm_device *dev)
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void intel_enable_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -5985,6 +5985,33 @@ void intel_init_clock_gating(struct drm_device *dev)
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}
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}
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void intel_disable_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->renderctx) {
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struct drm_i915_gem_object *obj = dev_priv->renderctx;
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I915_WRITE(CCID, 0);
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POSTING_READ(CCID);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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dev_priv->renderctx = NULL;
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}
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if (dev_priv->pwrctx) {
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struct drm_i915_gem_object *obj = dev_priv->pwrctx;
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I915_WRITE(PWRCTXA, 0);
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POSTING_READ(PWRCTXA);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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dev_priv->pwrctx = NULL;
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}
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}
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/* Set up chip specific display functions */
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static void intel_init_display(struct drm_device *dev)
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{
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@ -6211,7 +6238,7 @@ void intel_modeset_init(struct drm_device *dev)
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intel_setup_outputs(dev);
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intel_init_clock_gating(dev);
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intel_enable_clock_gating(dev);
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/* Just disable it once at startup */
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i915_disable_vga(dev);
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@ -6252,31 +6279,11 @@ void intel_modeset_cleanup(struct drm_device *dev)
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if (dev_priv->display.disable_fbc)
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dev_priv->display.disable_fbc(dev);
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if (dev_priv->renderctx) {
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struct drm_i915_gem_object *obj = dev_priv->renderctx;
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I915_WRITE(CCID, obj->gtt_offset &~ CCID_EN);
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POSTING_READ(CCID);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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dev_priv->renderctx = NULL;
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}
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if (dev_priv->pwrctx) {
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struct drm_i915_gem_object *obj = dev_priv->pwrctx;
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I915_WRITE(PWRCTXA, obj->gtt_offset &~ PWRCTX_EN);
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POSTING_READ(PWRCTXA);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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dev_priv->pwrctx = NULL;
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}
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if (IS_IRONLAKE_M(dev))
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ironlake_disable_drps(dev);
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intel_disable_clock_gating(dev);
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mutex_unlock(&dev->struct_mutex);
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/* Disable the irq before mode object teardown, for the irq might
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@ -294,7 +294,8 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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u16 blue, int regno);
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extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, int regno);
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extern void intel_init_clock_gating(struct drm_device *dev);
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extern void intel_enable_clock_gating(struct drm_device *dev);
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extern void intel_disable_clock_gating(struct drm_device *dev);
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extern void ironlake_enable_drps(struct drm_device *dev);
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extern void ironlake_disable_drps(struct drm_device *dev);
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extern void intel_init_emon(struct drm_device *dev);
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