redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

m68knommu: support version 2 ColdFire split cache

Browse source 
The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2010-11-09 15:31:08 +10:00
parent d475e3e473
commit 0ef6c9b8f7
2 changed files with 48 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
arch/m68k/include/asm/m52xxacr.h
View file

@ -53,23 +53,25 @@
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/*
* Set the cache controller settings we will use. This code is set to
* only use the instruction cache, even on the controllers that support
* split cache. (This setup is trying to preserve the existing behavior
* for now, in the furture I hope to actually use the split cache mode).
* Set the cache controller settings we will use. On the cores that support
* a split cache configuration we allow all the combinations at Kconfig
* time. For those cores that only have an instruction cache we just set
* that as on.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M5249) || defined(CONFIG_M5272)
#if defined(CONFIG_CACHE_I)
#define CACHE_TYPE CACR_DISD
#elif defined(CONFIG_CACHE_D)
#define CACHE_TYPE CACR_DISI
#else
#define CACHE_TYPE
#endif
#if defined(CONFIG_HAVE_CACHE_SPLIT)
#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP)
#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP)
#else
#define CACHE_INIT (CACR_CINV)
#define CACHE_MODE (CACR_CENB + CACR_DCM)
#else
#ifdef CONFIG_COLDFIRE_SW_A7
#define CACHE_INIT (CACR_CINV + CACR_DISD)
#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM)
#else
#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP)
#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
#endif
#endif
#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)

32
arch/m68knommu/Kconfig
View file

@ -79,6 +79,9 @@ config COLDFIRE_SW_A7
bool
default n
config HAVE_CACHE_SPLIT
bool
source "init/Kconfig"
source "kernel/Kconfig.freezer"
@ -124,12 +127,14 @@ config M5206e
config M520x
bool "MCF520x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Freescale Coldfire 5207/5208 processor support.
config M523x
bool "MCF523x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Freescale Coldfire 5230/1/2/4/5 processor support
@ -141,6 +146,7 @@ config M5249
config M5271
bool "MCF5271"
select HAVE_CACHE_SPLIT
help
Freescale (Motorola) ColdFire 5270/5271 processor support.
@ -152,12 +158,14 @@ config M5272
config M5275
bool "MCF5275"
select HAVE_CACHE_SPLIT
help
Freescale (Motorola) ColdFire 5274/5275 processor support.
config M528x
bool "MCF528x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
Motorola ColdFire 5280/5282 processor support.
@ -250,6 +258,30 @@ config OLDMASK
Build support for the older revision ColdFire 5307 silicon.
Specifically this is the 1H55J mask revision.
if HAVE_CACHE_SPLIT
choice
prompt "Split Cache Configuration"
default CACHE_I
config CACHE_I
bool "Instruction"
help
Use all of the ColdFire CPU cache memory as an instruction cache.
config CACHE_D
bool "Data"
help
Use all of the ColdFire CPU cache memory as a data cache.
config CACHE_BOTH
bool "Both"
help
Split the ColdFire CPU cache, and use half as an instruction cache
and half as a data cache.
endchoice
endif
comment "Platform"
config PILOT3