drm/radeon: implement UVD hw workarounds for R6xx v3
Only the essentials, cause this hw generation is really buggy. v2: start supporting RV670,RV620 and RV635 as well v3: activate more workarounds Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -330,6 +330,7 @@
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#define HDP_TILING_CONFIG 0x2F3C
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#define HDP_DEBUG1 0x2F34
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#define MC_CONFIG 0x2000
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#define MC_VM_AGP_TOP 0x2184
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#define MC_VM_AGP_BOT 0x2188
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#define MC_VM_AGP_BASE 0x218C
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@ -375,6 +376,8 @@
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#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
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#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
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#define RS_DQ_RD_RET_CONF 0x2348
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#define PA_CL_ENHANCE 0x8A14
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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@ -207,8 +207,32 @@ done:
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/* lower clocks again */
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radeon_set_uvd_clocks(rdev, 0, 0);
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if (!r)
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if (!r) {
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switch (rdev->family) {
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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/* 64byte granularity workaround */
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WREG32(MC_CONFIG, 0);
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WREG32(MC_CONFIG, 1 << 4);
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WREG32(RS_DQ_RD_RET_CONF, 0x3f);
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WREG32(MC_CONFIG, 0x1f);
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/* fall through */
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case CHIP_RV670:
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case CHIP_RV635:
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/* write clean workaround */
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WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
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break;
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default:
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/* TODO: Do we need more? */
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break;
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}
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DRM_INFO("UVD initialized successfully.\n");
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}
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return r;
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}
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