drm/radeon: add UVD support for older asics v4
v2: cleanup R600 support v3: rebased on current drm-fixes-3.12 v4: rebased on drm-next-3.14 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3009,6 +3009,17 @@ static int r600_startup(struct radeon_device *rdev)
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return r;
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}
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r = uvd_v1_0_resume(rdev);
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if (!r) {
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r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
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}
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}
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if (r) {
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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}
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/* Enable IRQ */
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if (!rdev->irq.installed) {
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r = radeon_irq_kms_init(rdev);
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@ -3037,6 +3048,16 @@ static int r600_startup(struct radeon_device *rdev)
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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RADEON_CP_PACKET2);
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if (!r)
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r = uvd_v1_0_init(rdev);
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if (r)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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}
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -3096,6 +3117,8 @@ int r600_suspend(struct radeon_device *rdev)
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radeon_pm_suspend(rdev);
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r600_audio_fini(rdev);
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r600_cp_stop(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_suspend(rdev);
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r600_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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r600_pcie_gart_disable(rdev);
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@ -3175,6 +3198,12 @@ int r600_init(struct radeon_device *rdev)
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
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r = radeon_uvd_init(rdev);
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if (!r) {
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
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}
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -3204,6 +3233,8 @@ void r600_fini(struct radeon_device *rdev)
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r600_audio_fini(rdev);
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r600_cp_fini(rdev);
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r600_irq_fini(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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@ -1485,6 +1485,7 @@
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#define UVD_CGC_GATE 0xf4a8
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#define UVD_LMI_CTRL2 0xf4f4
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#define UVD_MASTINT_EN 0xf500
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#define UVD_FW_START 0xf51C
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#define UVD_LMI_ADDR_EXT 0xf594
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#define UVD_LMI_CTRL 0xf598
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#define UVD_LMI_SWAP_CNTL 0xf5b4
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@ -1497,6 +1498,13 @@
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#define UVD_MPC_SET_MUX 0xf5f4
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#define UVD_MPC_SET_ALU 0xf5f8
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#define UVD_VCPU_CACHE_OFFSET0 0xf608
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#define UVD_VCPU_CACHE_SIZE0 0xf60c
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#define UVD_VCPU_CACHE_OFFSET1 0xf610
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#define UVD_VCPU_CACHE_SIZE1 0xf614
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#define UVD_VCPU_CACHE_OFFSET2 0xf618
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#define UVD_VCPU_CACHE_SIZE2 0xf61c
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#define UVD_VCPU_CNTL 0xf660
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#define UVD_SOFT_RESET 0xf680
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#define RBC_SOFT_RESET (1<<0)
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@ -965,6 +965,19 @@ static struct radeon_asic r600_asic = {
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},
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};
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static struct radeon_asic_ring rv6xx_uvd_ring = {
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.ib_execute = &uvd_v1_0_ib_execute,
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.emit_fence = &uvd_v1_0_fence_emit,
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.emit_semaphore = &uvd_v1_0_semaphore_emit,
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.cs_parse = &radeon_uvd_cs_parse,
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.ring_test = &uvd_v1_0_ring_test,
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.ib_test = &uvd_v1_0_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &uvd_v1_0_get_rptr,
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.get_wptr = &uvd_v1_0_get_wptr,
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.set_wptr = &uvd_v1_0_set_wptr,
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};
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static struct radeon_asic rv6xx_asic = {
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.init = &r600_init,
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.fini = &r600_fini,
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@ -984,6 +997,7 @@ static struct radeon_asic rv6xx_asic = {
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.ring = {
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[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
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[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
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},
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.irq = {
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.set = &r600_irq_set,
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@ -1074,6 +1088,7 @@ static struct radeon_asic rs780_asic = {
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.ring = {
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[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
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[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
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},
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.irq = {
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.set = &r600_irq_set,
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@ -883,6 +883,7 @@ uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void uvd_v1_0_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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int uvd_v1_0_resume(struct radeon_device *rdev);
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int uvd_v1_0_init(struct radeon_device *rdev);
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void uvd_v1_0_fini(struct radeon_device *rdev);
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@ -890,6 +891,8 @@ int uvd_v1_0_start(struct radeon_device *rdev);
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void uvd_v1_0_stop(struct radeon_device *rdev);
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int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
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void uvd_v1_0_fence_emit(struct radeon_device *rdev,
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struct radeon_fence *fence);
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int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
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bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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@ -22,6 +22,7 @@
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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@ -69,6 +70,82 @@ void uvd_v1_0_set_wptr(struct radeon_device *rdev,
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WREG32(UVD_RBC_RB_WPTR, ring->wptr);
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}
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/**
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* uvd_v1_0_fence_emit - emit an fence & trap command
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*
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* @rdev: radeon_device pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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void uvd_v1_0_fence_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, addr & 0xffffffff);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
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radeon_ring_write(ring, 2);
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return;
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}
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/**
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* uvd_v1_0_resume - memory controller programming
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*
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* @rdev: radeon_device pointer
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*
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* Let the UVD memory controller know it's offsets
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*/
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int uvd_v1_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr;
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uint32_t size;
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int r;
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r = radeon_uvd_resume(rdev);
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if (r)
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return r;
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/* programm the VCPU memory controller bits 0-27 */
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addr = (rdev->uvd.gpu_addr >> 3) + 16;
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size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
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WREG32(UVD_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = RADEON_UVD_STACK_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
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WREG32(UVD_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = RADEON_UVD_HEAP_SIZE >> 3;
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WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
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WREG32(UVD_VCPU_CACHE_SIZE2, size);
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/* bits 28-31 */
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addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
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WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
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/* bits 32-39 */
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addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
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WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
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return 0;
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}
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/**
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* uvd_v1_0_init - start and test UVD block
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*
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@ -72,6 +72,10 @@ int uvd_v2_2_resume(struct radeon_device *rdev)
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uint32_t chip_id, size;
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int r;
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/* RV770 uses V1.0 MC */
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if (rdev->family == CHIP_RV770)
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return uvd_v1_0_resume(rdev);
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r = radeon_uvd_resume(rdev);
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if (r)
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return r;
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