drm/radeon: add set_uvd_clocks callback for r6xx v4
v2: wake up PLL, set [VD]CLK_SRC, cleanup code v3: handle RV670,RV635,RV620 as well v4: merge rv6xx and rs780/rs880 code, fix ref divider mask Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
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@ -122,6 +122,94 @@ u32 r600_get_xclk(struct radeon_device *rdev)
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int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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{
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unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
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int r;
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
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UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
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if (rdev->family >= CHIP_RS780)
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WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
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~UPLL_BYPASS_CNTL);
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if (!vclk || !dclk) {
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/* keep the Bypass mode, put PLL to sleep */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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return 0;
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}
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if (rdev->clock.spll.reference_freq == 10000)
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ref_div = 34;
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else
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ref_div = 4;
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r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
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ref_div + 1, 0xFFF, 2, 30, ~0,
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&fb_div, &vclk_div, &dclk_div);
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if (r)
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return r;
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if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
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fb_div >>= 1;
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else
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fb_div |= 1;
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r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
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if (r)
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return r;
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/* assert PLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
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/* For RS780 we have to choose ref clk */
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if (rdev->family >= CHIP_RS780)
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
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~UPLL_REFCLK_SRC_SEL_MASK);
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/* set the required fb, ref and post divder values */
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WREG32_P(CG_UPLL_FUNC_CNTL,
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UPLL_FB_DIV(fb_div) |
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UPLL_REF_DIV(ref_div),
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~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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UPLL_SW_HILEN(vclk_div >> 1) |
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UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
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UPLL_SW_HILEN2(dclk_div >> 1) |
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UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
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UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
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~UPLL_SW_MASK);
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/* give the PLL some time to settle */
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mdelay(15);
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/* deassert PLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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mdelay(15);
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/* deassert BYPASS EN */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
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if (rdev->family >= CHIP_RS780)
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WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
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r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
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if (r)
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return r;
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/* switch VCLK and DCLK selection */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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mdelay(100);
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return 0;
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}
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@ -1526,9 +1526,35 @@
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#define UVD_CONTEXT_ID 0xf6f4
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/* rs780 only */
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#define GFX_MACRO_BYPASS_CNTL 0x30c0
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#define SPLL_BYPASS_CNTL (1 << 0)
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#define UPLL_BYPASS_CNTL (1 << 1)
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#define CG_UPLL_FUNC_CNTL 0x7e0
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# define UPLL_RESET_MASK 0x00000001
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# define UPLL_SLEEP_MASK 0x00000002
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# define UPLL_BYPASS_EN_MASK 0x00000004
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# define UPLL_CTLREQ_MASK 0x00000008
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# define UPLL_FB_DIV(x) ((x) << 4)
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# define UPLL_FB_DIV_MASK 0x0000FFF0
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# define UPLL_REF_DIV(x) ((x) << 16)
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# define UPLL_REF_DIV_MASK 0x003F0000
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# define UPLL_REFCLK_SRC_SEL_MASK 0x20000000
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# define UPLL_CTLACK_MASK 0x40000000
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# define UPLL_CTLACK2_MASK 0x80000000
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#define CG_UPLL_FUNC_CNTL_2 0x7e4
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# define UPLL_SW_HILEN(x) ((x) << 0)
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# define UPLL_SW_LOLEN(x) ((x) << 4)
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# define UPLL_SW_HILEN2(x) ((x) << 8)
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# define UPLL_SW_LOLEN2(x) ((x) << 12)
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# define UPLL_DIVEN_MASK 0x00010000
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# define UPLL_DIVEN2_MASK 0x00020000
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# define UPLL_SW_MASK 0x0003FFFF
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# define VCLK_SRC_SEL(x) ((x) << 20)
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# define VCLK_SRC_SEL_MASK 0x01F00000
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# define DCLK_SRC_SEL(x) ((x) << 25)
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# define DCLK_SRC_SEL_MASK 0x3E000000
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/*
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* PM4
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