drm/i915: Split g4x_crtc_compute_clock()
Split a G4X specific version from i9xx_crtc_compute_clock(). With this the differences between platforms become more obvious. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-15-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -564,28 +564,6 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
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return false;
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}
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static const intel_limit_t *
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intel_g4x_limit(struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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const intel_limit_t *limit;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_is_dual_link_lvds(dev))
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limit = &intel_limits_g4x_dual_channel_lvds;
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else
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limit = &intel_limits_g4x_single_channel_lvds;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
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intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
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limit = &intel_limits_g4x_hdmi;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
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limit = &intel_limits_g4x_sdvo;
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} else /* The option is for other outputs */
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limit = &intel_limits_i9xx_sdvo;
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return limit;
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}
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static const intel_limit_t *
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intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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{
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@ -593,12 +571,10 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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const intel_limit_t *limit;
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if (IS_BROXTON(dev) || IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev) ||
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HAS_PCH_SPLIT(dev) || IS_GEN2(dev))
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HAS_PCH_SPLIT(dev) || IS_G4X(dev) || IS_GEN2(dev))
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limit = NULL;
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if (IS_G4X(dev)) {
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limit = intel_g4x_limit(crtc_state);
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} else if (IS_PINEVIEW(dev)) {
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if (IS_PINEVIEW(dev)) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_pineview_lvds;
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else
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@ -7830,6 +7806,49 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
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return 0;
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}
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static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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int refclk = 96000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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}
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if (intel_is_dual_link_lvds(dev))
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limit = &intel_limits_g4x_dual_channel_lvds;
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else
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limit = &intel_limits_g4x_single_channel_lvds;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
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intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
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limit = &intel_limits_g4x_hdmi;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
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limit = &intel_limits_g4x_sdvo;
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} else {
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/* The option is for other outputs */
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limit = &intel_limits_i9xx_sdvo;
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}
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if (!crtc_state->clock_set &&
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!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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return 0;
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}
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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@ -14781,9 +14800,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
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*/
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void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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{
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if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
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dev_priv->display.find_dpll = g4x_find_best_dpll;
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else if (IS_PINEVIEW(dev_priv))
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if (IS_PINEVIEW(dev_priv))
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dev_priv->display.find_dpll = pnv_find_best_dpll;
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else
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dev_priv->display.find_dpll = i9xx_find_best_dpll;
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@ -14826,6 +14843,13 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else if (IS_G4X(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else if (!IS_GEN2(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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