drm/i915: Split i8xx_crtc_compute_clock()
Split a GEN2 specific version from i9xx_crtc_compute_clock(). With this there is no need for i9xx_get_refclk() anymore, and the differences between platforms become more obvious. v2: Use i8xx as prefix instead of gen2. (Ville and Daniel) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458653723-17951-1-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -593,7 +593,7 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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const intel_limit_t *limit;
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if (IS_BROXTON(dev) || IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev) ||
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HAS_PCH_SPLIT(dev))
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HAS_PCH_SPLIT(dev) || IS_GEN2(dev))
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limit = NULL;
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if (IS_G4X(dev)) {
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@ -608,13 +608,6 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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limit = &intel_limits_i9xx_lvds;
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else
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limit = &intel_limits_i9xx_sdvo;
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} else {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_i8xx_lvds;
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else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
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limit = &intel_limits_i8xx_dvo;
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else
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limit = &intel_limits_i8xx_dac;
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}
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WARN_ON(limit == NULL);
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@ -7047,27 +7040,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
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}
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk;
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WARN_ON(!crtc_state->base.state);
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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} else if (!IS_GEN2(dev)) {
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refclk = 96000;
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} else {
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refclk = 48000;
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}
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return refclk;
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}
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static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
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{
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return (1 << dpll->n) << 16 | dpll->m2;
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@ -7822,14 +7794,50 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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POSTING_READ(PIPECONF(intel_crtc->pipe));
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}
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static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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int refclk = 48000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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}
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limit = &intel_limits_i8xx_lvds;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
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limit = &intel_limits_i8xx_dvo;
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} else {
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limit = &intel_limits_i8xx_dac;
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}
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if (!crtc_state->clock_set &&
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!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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i8xx_compute_dpll(crtc, crtc_state, NULL);
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return 0;
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}
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk;
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bool ok;
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const intel_limit_t *limit;
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int refclk = 96000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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@ -7837,9 +7845,13 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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if (crtc_state->has_dsi_encoder)
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return 0;
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if (!crtc_state->clock_set) {
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refclk = i9xx_get_refclk(crtc_state);
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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}
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if (!crtc_state->clock_set) {
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/*
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* Returns a set of divisors for the desired target clock with
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* the given refclk, or FALSE. The returned values represent
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@ -7857,11 +7869,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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}
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}
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if (IS_GEN2(dev)) {
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i8xx_compute_dpll(crtc, crtc_state, NULL);
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} else {
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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}
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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return 0;
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}
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@ -14818,13 +14826,20 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else {
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} else if (!IS_GEN2(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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}
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/* Returns the core display clock speed */
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