drm/i915: Split CHV and VLV specific crtc_compute_clock() hooks
In order for VLV and CHV to use i9xx_crtc_compute_clocks(), a number of if ladders is necessary: one for setting the find_dpll() hook, one for choosing the limits struct, one for choosing the right compute dpll function and one for initializing the crtc_compute_clock() hook. By extracting a platform specific implementation for each platform, the number of if-ladders is reduced to one. While at it also clean up bxt_find_best_dpll() which depends on some of the CHV code. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-13-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -111,7 +111,6 @@ static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
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static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
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static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state);
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state);
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static void skylake_pfit_enable(struct intel_crtc *crtc);
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static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
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static void ironlake_pfit_enable(struct intel_crtc *crtc);
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@ -593,21 +592,17 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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struct drm_device *dev = crtc_state->base.crtc->dev;
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const intel_limit_t *limit;
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if (IS_BROXTON(dev))
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limit = &intel_limits_bxt;
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else if (WARN_ON(HAS_PCH_SPLIT(dev)))
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if (IS_BROXTON(dev) || IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev) ||
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HAS_PCH_SPLIT(dev))
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limit = NULL;
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else if (IS_G4X(dev)) {
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if (IS_G4X(dev)) {
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limit = intel_g4x_limit(crtc_state);
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} else if (IS_PINEVIEW(dev)) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_pineview_lvds;
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else
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limit = &intel_limits_pineview_sdvo;
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} else if (IS_CHERRYVIEW(dev)) {
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limit = &intel_limits_chv;
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} else if (IS_VALLEYVIEW(dev)) {
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limit = &intel_limits_vlv;
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} else if (!IS_GEN2(dev)) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_i9xx_lvds;
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@ -621,6 +616,9 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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else
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limit = &intel_limits_i8xx_dac;
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}
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WARN_ON(limit == NULL);
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return limit;
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}
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@ -939,6 +937,11 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
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return *error_ppm + 10 < best_error_ppm;
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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static bool
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vlv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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@ -993,6 +996,11 @@ vlv_find_best_dpll(const intel_limit_t *limit,
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return found;
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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static bool
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chv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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@ -1054,9 +1062,10 @@ chv_find_best_dpll(const intel_limit_t *limit,
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
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intel_clock_t *best_clock)
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{
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int refclk = i9xx_get_refclk(crtc_state);
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int refclk = 100000;
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const intel_limit_t *limit = &intel_limits_bxt;
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return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
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return chv_find_best_dpll(limit, crtc_state,
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target_clock, refclk, NULL, best_clock);
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}
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@ -7046,9 +7055,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state)
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WARN_ON(!crtc_state->base.state);
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if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
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refclk = 100000;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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@ -7852,10 +7859,6 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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if (IS_GEN2(dev)) {
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i8xx_compute_dpll(crtc, crtc_state, NULL);
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} else if (IS_CHERRYVIEW(dev)) {
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chv_compute_dpll(crtc, crtc_state);
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} else if (IS_VALLEYVIEW(dev)) {
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vlv_compute_dpll(crtc, crtc_state);
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} else {
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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}
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@ -7863,6 +7866,54 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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return 0;
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}
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static int chv_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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int refclk = 100000;
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const intel_limit_t *limit = &intel_limits_chv;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (crtc_state->has_dsi_encoder)
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return 0;
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if (!crtc_state->clock_set &&
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!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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chv_compute_dpll(crtc, crtc_state);
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return 0;
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}
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static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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int refclk = 100000;
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const intel_limit_t *limit = &intel_limits_vlv;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (crtc_state->has_dsi_encoder)
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return 0;
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if (!crtc_state->clock_set &&
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!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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vlv_compute_dpll(crtc, crtc_state);
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return 0;
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}
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static void i9xx_get_pfit_config(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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@ -14724,10 +14775,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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{
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if (HAS_PCH_SPLIT(dev_priv) || IS_G4X(dev_priv))
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dev_priv->display.find_dpll = g4x_find_best_dpll;
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else if (IS_CHERRYVIEW(dev_priv))
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dev_priv->display.find_dpll = chv_find_best_dpll;
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else if (IS_VALLEYVIEW(dev_priv))
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dev_priv->display.find_dpll = vlv_find_best_dpll;
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else if (IS_PINEVIEW(dev_priv))
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dev_priv->display.find_dpll = pnv_find_best_dpll;
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else
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@ -14757,11 +14804,18 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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ironlake_crtc_compute_clock;
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dev_priv->display.crtc_enable = ironlake_crtc_enable;
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dev_priv->display.crtc_disable = ironlake_crtc_disable;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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} else if (IS_CHERRYVIEW(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else if (IS_VALLEYVIEW(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else {
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