drm/i915: Merge ironlake_compute_clocks() and ironlake_crtc_compute_clock()
Merge ironlake_compute_clocks() into ironlake_crtc_compute_clock() so the clock computation logic is all in one place. The resulting function is still quite simple. Follow up patches will make the similar code for GMCH platforms look similar. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-12-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -846,6 +846,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
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return (err != target);
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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static bool
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g4x_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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@ -8628,55 +8633,6 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
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}
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}
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static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *clock,
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bool *has_reduced_clock,
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk;
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const intel_limit_t *limit;
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bool ret;
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refclk = 120000;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
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dev_priv->vbt.lvds_ssc_freq);
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refclk = dev_priv->vbt.lvds_ssc_freq;
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}
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if (intel_is_dual_link_lvds(dev)) {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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else
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limit = &intel_limits_ironlake_dual_lvds;
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} else {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_single_lvds_100m;
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else
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limit = &intel_limits_ironlake_single_lvds;
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}
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} else {
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limit = &intel_limits_ironlake_dac;
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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ret = g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, clock);
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if (!ret)
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return false;
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return true;
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}
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int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
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{
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/*
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@ -8801,9 +8757,13 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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intel_clock_t reduced_clock;
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bool has_reduced_clock = false;
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struct intel_shared_dpll *pll;
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const intel_limit_t *limit;
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int refclk = 120000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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@ -8814,11 +8774,31 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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if (!crtc_state->has_pch_encoder)
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return 0;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
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dev_priv->vbt.lvds_ssc_freq);
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refclk = dev_priv->vbt.lvds_ssc_freq;
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}
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if (intel_is_dual_link_lvds(dev)) {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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else
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limit = &intel_limits_ironlake_dual_lvds;
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} else {
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if (refclk == 100000)
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limit = &intel_limits_ironlake_single_lvds_100m;
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else
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limit = &intel_limits_ironlake_single_lvds;
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}
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} else {
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limit = &intel_limits_ironlake_dac;
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}
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if (!crtc_state->clock_set &&
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!ironlake_compute_clocks(&crtc->base, crtc_state,
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&crtc_state->dpll,
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&has_reduced_clock,
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&reduced_clock)) {
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!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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