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MLK-24171-1 arm64: dts: imx8mp: verify the pcie pll sys ref clock 

Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Richard Zhu 2020-05-27 10:11:08 +08:00
parent 30f393c50b
commit 1bda33273e
2 changed files with 4 additions and 3 deletions
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5
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -674,7 +674,7 @@
pinctrl-0 = <&pinctrl_pcie>;
disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
ext_osc = <0>;
ext_osc = <1>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
<&clk IMX8MP_CLK_PCIE_AUX>,
<&clk IMX8MP_CLK_PCIE_PHY>,
@ -691,7 +691,7 @@
&pcie_ep{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
ext_osc = <0>;
ext_osc = <1>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
<&clk IMX8MP_CLK_PCIE_AUX>,
<&clk IMX8MP_CLK_PCIE_PHY>,
@ -705,6 +705,7 @@
};
&pcie_phy{
ext_osc = <1>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1936,7 +1936,7 @@
<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <3>;
fsl,max-link-speed = <2>;
power-domains = <&pcie_pd>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIEPHY_PERST>,