MLK-23925: dts: arm64: freescale: imx8mn audio board
iMX8MN DDR4 and LPDDR4 SOM on Audio Board 2.0 enable base support, ADC and SPDIF. Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>5.4-rM2-2.2.x-imx-squashed
Adrian Alonso
parent
6f6ce7b7ad
commit
1d631c17d7
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@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.
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imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \
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imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb imx8mn-evk-root.dtb imx8mn-evk-inmate.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ab2.dtb imx8mn-ddr4-ab2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \
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imx8mp-evk-rm67191.dtb imx8mp-evk-flexcan2.dtb imx8mp-evk-it6263-lvds-dual-channel.dtb \
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imx8mp-evk-jdi-wuxga-lvds-panel.dtb imx8mp-ab2.dtb imx8mp-evk-sof-wm8960.dtb \
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@ -0,0 +1,829 @@
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/*
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* Copyright 2020 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx8mn.dtsi"
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/ {
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model = "NXP i.MX8MNano Audio board 2.0";
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compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
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chosen {
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bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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status {
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label = "status";
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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panel {
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label = "panel";
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gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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modem_reset: modem-reset {
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compatible = "gpio-reset";
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reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2000>;
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reset-post-delay-ms = <40>;
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#reset-cells = <0>;
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};
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usdhc1_pwrseq: usdhc1_pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1_gpio>;
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
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compatible = "regulator-fixed";
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regulator-name = "ab2_ana_pwr";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "ab2_vdd_pwr_5v0";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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};
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sound-ak5552 {
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compatible = "fsl,imx-audio-ak5558";
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model = "ak5552-audio";
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audio-cpu = <&sai3>;
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audio-codec = <&ak5552>;
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif1>;
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spdif-out;
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spdif-in;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&clk {
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assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>;
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assigned-clock-rates = <393216000>, <361267200>;
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};
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&easrc {
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fsl,asrc-rate = <48000>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx8mn-ab2 {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
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>;
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};
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pinctrl_flexspi0: flexspi0grp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
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MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
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MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
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MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
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MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
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MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
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>;
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};
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pinctrl_gpio_led: gpioledgrp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
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MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
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MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
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>;
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};
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pinctrl_ecspi2_cs: ecspi2cs {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
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MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp-gpio {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
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MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
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>;
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};
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pinctrl_i2c2_gpio: i2c2grp-gpio {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
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MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
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>;
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};
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pinctrl_i2c3_gpio: i2c3grp-gpio {
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fsl,pins = <
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MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
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MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
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>;
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};
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pinctrl_pmic: pmicirq {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_ab2_ana_pwr: ab2anapwrgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
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>;
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};
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pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
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MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
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MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
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>;
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};
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pinctrl_spdif1: spdif1grp {
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fsl,pins = <
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MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
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MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
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MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
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MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
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MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
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MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
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MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
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>;
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};
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pinctrl_usdhc1_gpio: usdhc1grpgpio {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan: wlangrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
|
||||
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mipi_dsi_en: mipi_dsi_en {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: mt25qu256aba@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <80000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
|
||||
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
spidev0: spi@0 {
|
||||
reg = <0>;
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pca9450@25 {
|
||||
reg = <0x25>;
|
||||
compatible = "nxp,pca9450";
|
||||
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pca9450,pmic-buck2-uses-i2c-dvs;
|
||||
/* Run/Standby voltage */
|
||||
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
|
||||
|
||||
buck1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "buck1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "buck2";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "buck3";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "buck4";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "buck5";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "buck6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
adv_bridge: adv7535@3d {
|
||||
compatible = "adi,adv7533";
|
||||
reg = <0x3d>;
|
||||
adi,addr-cec = <0x3b>;
|
||||
adi,dsi-lanes = <4>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
adv7535_from_dsim: endpoint {
|
||||
remote-endpoint = <&dsim_to_adv7535>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pca6408_2: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
pca6416_2: gpio@21 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
||||
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
ak5552: ak5552@13 {
|
||||
compatible = "asahi-kasei,ak5552";
|
||||
reg = <0x13>;
|
||||
reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-post-delay = <150>;
|
||||
phy-reset-duration = <10>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
eee-broken-1000t;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "okay";
|
||||
|
||||
port@1 {
|
||||
dsim_to_adv7535: endpoint {
|
||||
remote-endpoint = <&adv7535_from_dsim>;
|
||||
attach-bridge;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 { /* BT */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
|
||||
fsl,uart-has-rtscts;
|
||||
resets = <&modem_reset>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdif1>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
|
||||
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>,
|
||||
<&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>;
|
||||
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
|
||||
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
|
||||
bus-width = <4>;
|
||||
pm-ignore-notify;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
/delete-property/ vmmc-supply;
|
||||
mmc-pwrseq = <&usdhc1_pwrseq>;
|
||||
status = "okay";
|
||||
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,752 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx8mn.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MNano DDR4 Audio board 2.0";
|
||||
compatible = "fsl,imx8mn-ddr4-ab2", "fsl,imx8mn";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_led>;
|
||||
|
||||
status {
|
||||
label = "status";
|
||||
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
panel {
|
||||
label = "panel";
|
||||
gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
modem_reset: modem-reset {
|
||||
compatible = "gpio-reset";
|
||||
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2000>;
|
||||
reset-post-delay-ms = <40>;
|
||||
#reset-cells = <0>;
|
||||
};
|
||||
|
||||
usdhc1_pwrseq: usdhc1_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1_gpio>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
off-on-delay-us = <12000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ab2_ana_pwr";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ab2_vdd_pwr_5v0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound-ak5552 {
|
||||
compatible = "fsl,imx-audio-ak5558";
|
||||
model = "ak5552-audio";
|
||||
audio-cpu = <&sai3>;
|
||||
audio-codec = <&ak5552>;
|
||||
};
|
||||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
spdif-controller = <&spdif1>;
|
||||
spdif-out;
|
||||
spdif-in;
|
||||
};
|
||||
};
|
||||
|
||||
&clk {
|
||||
assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>;
|
||||
assigned-clock-rates = <393216000>, <361267200>;
|
||||
};
|
||||
|
||||
&easrc {
|
||||
fsl,asrc-rate = <48000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
|
||||
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
|
||||
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
|
||||
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
|
||||
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
|
||||
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mipi_dsi_en: mipi_dsi_en {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirq {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ab2_ana_pwr: ab2anapwrgrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2grp-gpio {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
|
||||
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3grp-gpio {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
|
||||
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
||||
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
||||
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
|
||||
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif1: spdif1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
|
||||
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
|
||||
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
|
||||
MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
|
||||
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
|
||||
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
|
||||
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wlan: wlangrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
|
||||
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
adv_bridge: adv7535@3d {
|
||||
compatible = "adi,adv7533";
|
||||
reg = <0x3d>;
|
||||
adi,addr-cec = <0x3b>;
|
||||
adi,dsi-lanes = <4>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
adv7535_from_dsim: endpoint {
|
||||
remote-endpoint = <&dsim_to_adv7535>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pca6408_2: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck4_reg>;
|
||||
};
|
||||
|
||||
pca6416_2: gpio@21 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
||||
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
ak5552: ak5552@13 {
|
||||
compatible = "asahi-kasei,ak5552";
|
||||
reg = <0x13>;
|
||||
reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-post-delay = <150>;
|
||||
phy-reset-duration = <10>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
eee-broken-1000t;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: mt25qu256aba@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <80000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71847";
|
||||
reg = <0x4b>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
|
||||
regulators {
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
rohm,dvs-run-voltage = <1000000>;
|
||||
rohm,dvs-idle-voltage = <900000>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "okay";
|
||||
|
||||
port@1 {
|
||||
dsim_to_adv7535: endpoint {
|
||||
remote-endpoint = <&adv7535_from_dsim>;
|
||||
attach-bridge;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 { /* BT */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
|
||||
fsl,uart-has-rtscts;
|
||||
resets = <&modem_reset>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
|
||||
bus-width = <4>;
|
||||
pm-ignore-notify;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
/delete-property/ vmmc-supply;
|
||||
mmc-pwrseq = <&usdhc1_pwrseq>;
|
||||
status = "okay";
|
||||
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
|
||||
<&clk IMX8MN_CLK_GPU_SHADER_SRC>,
|
||||
<&clk IMX8MN_CLK_GPU_AXI>,
|
||||
<&clk IMX8MN_CLK_GPU_AHB>,
|
||||
<&clk IMX8MN_GPU_PLL>,
|
||||
<&clk IMX8MN_CLK_GPU_CORE_DIV>,
|
||||
<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
|
||||
assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
|
||||
<&clk IMX8MN_GPU_PLL_OUT>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
|
||||
<400000000>, <400000000>;
|
||||
status= "okay";
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
|
||||
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdif1>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
|
||||
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>,
|
||||
<&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>;
|
||||
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
|
||||
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue