drm/i915/skl: Framebuffers need to be aligned to 256KB on Skylake
v2: Also align X tiled fbs to 256KB (Thomas) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2199,7 +2199,9 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
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switch (obj->tiling_mode) {
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case I915_TILING_NONE:
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if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
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if (INTEL_INFO(dev)->gen >= 9)
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alignment = 256 * 1024;
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else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
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alignment = 128 * 1024;
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else if (INTEL_INFO(dev)->gen >= 4)
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alignment = 4 * 1024;
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@ -2207,8 +2209,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
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alignment = 64 * 1024;
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break;
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case I915_TILING_X:
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/* pin() will align the object as required by fence */
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alignment = 0;
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if (INTEL_INFO(dev)->gen >= 9)
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alignment = 256 * 1024;
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else {
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/* pin() will align the object as required by fence */
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alignment = 0;
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}
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break;
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case I915_TILING_Y:
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WARN(1, "Y tiled bo slipped through, driver bug!\n");
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