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drm/i915/skl: Framebuffers need to be aligned to 256KB on Skylake

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v2: Also align X tiled fbs to 256KB (Thomas)

Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2013-07-03 21:06:02 +01:00 committed by Daniel Vetter
parent fbdcb06880
commit 1fada4cc6a
1 changed files with 9 additions and 3 deletions
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12
drivers/gpu/drm/i915/intel_display.c
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@ -2199,7 +2199,9 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
switch (obj->tiling_mode) {
case I915_TILING_NONE:
if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
if (INTEL_INFO(dev)->gen >= 9)
alignment = 256 * 1024;
else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
alignment = 128 * 1024;
else if (INTEL_INFO(dev)->gen >= 4)
alignment = 4 * 1024;
@ -2207,8 +2209,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
alignment = 64 * 1024;
break;
case I915_TILING_X:
/* pin() will align the object as required by fence */
alignment = 0;
if (INTEL_INFO(dev)->gen >= 9)
alignment = 256 * 1024;
else {
/* pin() will align the object as required by fence */
alignment = 0;
}
break;
case I915_TILING_Y:
WARN(1, "Y tiled bo slipped through, driver bug!\n");