MLK-23250-11: arm64: dts: imx: add imx8mp hdmimix modules
new dts file for imx8mp hdmi. Add all hdmimix submodules. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>5.4-rM2-2.2.x-imx-squashed
Sandor Yu
parent
b82d0af62f
commit
229661a121
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@ -40,7 +40,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.
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imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb imx8mp-evk-rpmsg.dtb \
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imx8mp-evk-rm67191.dtb
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imx8mp-evk-rm67191.dtb imx8mp-evk-hdmi.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb
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@ -0,0 +1,57 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include "imx8mp-evk.dts"
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/ {
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sound-aud2htx {
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status = "okay";
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&lcdif3_disp>;
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};
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};
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&mipi_dsi {
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status = "disabled";
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};
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&lcdif1 {
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status = "disabled";
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};
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&lcdif3 {
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status = "okay";
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};
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&irqsteer_hdmi {
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status = "okay";
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};
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&hdmimix_clk {
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status = "okay";
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};
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&hdmimix_reset {
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status = "okay";
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};
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&hdmi_pavi {
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status = "okay";
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};
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&hdmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi>;
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status = "okay";
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};
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&hdmiphy {
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status = "okay";
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};
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@ -898,6 +898,14 @@
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MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x59
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>;
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};
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pinctrl_hdmi: hdmigrp {
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fsl,pins = <
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MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3
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MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3
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MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019
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>;
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};
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};
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&vpu_g1 {
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@ -9,7 +9,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/reset/imx8mp-mediamix.h>
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#include <dt-bindings/reset/imx-hdmimix-reset.h>
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#include "imx8mp-pinfunc.h"
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/ {
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@ -1175,6 +1175,156 @@
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reg = <0x32ec0000 0x10000>;
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};
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/* TODO for HDMI PHY power on */
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hdmi_blk: hdmi-blk@32fc0000 {
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compatible = "syscon";
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reg = <0x32fc0000 0x1000>;
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};
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hdmimix: hdmimix@32fc0000 {
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compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix";
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reg = <0x32fc0000 0x1000>;
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hdmimix_clk: clock-controller {
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compatible = "fsl,imx8mp-hdmimix-clk";
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#clock-cells = <1>;
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clocks = <&clk IMX8MP_CLK_DUMMY>;
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clock-names = "dummy";
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status = "disabled";
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};
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hdmimix_reset: reset-controller {
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compatible = "fsl,imx8mp-hdmimix-reset";
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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irqsteer_hdmi: irqsteer@32fc2000 {
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compatible = "fsl,imx-irqsteer";
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reg = <0x32fc2000 0x1000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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fsl,channel = <1>;
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fsl,num-irqs = <64>;
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clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>;
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clock-names = "ipg";
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assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <200000000>;
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resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>;
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status = "disabled";
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};
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hdmi_pavi: hdmi-pai-pvi@32fc4000 {
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compatible = "fsl,imx8mp-hdmi-pavi";
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reg = <0x32fc4000 0x1000>;
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clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>;
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clock-names = "pvi_clk", "pai_clk";
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resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>,
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<&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>;
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reset-names = "pai_rst", "pvi_rst";
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status = "disabled";
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};
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lcdif3: lcd-controller@32fc6000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8mp-lcdif3";
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reg = <0x32fc6000 0x10000>;
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clocks = <&hdmiphy 0>,
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<&clk IMX8MP_CLK_HDMI_AXI>,
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<&clk IMX8MP_CLK_HDMI_APB>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>;
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clock-names = "pix", "disp-axi", "disp-apb",
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"mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb",
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"lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu",
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"noc_hdmi";
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assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
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<&clk IMX8MP_CLK_HDMI_APB>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <500000000>, <200000000>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&irqsteer_hdmi>;
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resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>;
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status = "disabled";
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lcdif3_disp: port@0 {
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reg = <0>;
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lcdif3_to_hdmi: endpoint {
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remote-endpoint = <&hdmi_from_lcdif3>;
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};
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};
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};
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hdmi: hdmi@32fd8000 {
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compatible = "fsl,imx8mp-hdmi";
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reg = <0x32fd8000 0x7eff>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&irqsteer_hdmi>;
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clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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<&clk IMX8MP_CLK_HDMI_24M>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>;
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clock-names = "iahb", "isfr",
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"phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk",
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"cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk";
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assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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<&clk IMX8MP_CLK_HDMI_AXI>,
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<&clk IMX8MP_CLK_HDMI_24M>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL2_500M>,
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<&clk IMX8MP_CLK_24M>;
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assigned-clock-rates = <200000000>, <500000000>, <24000000>;
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phys = <&hdmiphy>;
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phy-names = "hdmi";
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resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>;
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gpr = <&hdmi_blk>;
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power-domains = <&hdmi_phy_pd>;
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status = "disabled";
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port@0 {
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hdmi_from_lcdif3: endpoint {
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remote-endpoint = <&lcdif3_to_hdmi>;
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};
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};
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};
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hdmiphy: hdmiphy@32fdff00 {
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compatible = "fsl,samsung-hdmi-phy";
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reg = <0x32fdff00 0x100>;
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#clock-cells = <1>;
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clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>,
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<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>;
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clock-names = "apb", "ref";
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clock-output-names = "hdmi_phy";
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#phy-cells = <0>;
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resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>;
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status = "disabled";
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};
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mediamix_gasket0: gasket@32ec0060 {
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compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
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reg = <0x32ec0060 0x28>;
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