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irqchip: irq-imx-gpcv2: Disable cpuidle if no GPC_CORE_WAKE in EL3 

Not all EL3 have the FSL_SIP_CONFIG_GPC_CORE_WAKE, therefore disable
the cpuidle to avoid all the cores going to sleep ending up with a
hang. This allows all the EL3 implementations to work with i.MX8MQ
even if they do not support core wake-up through GPC as a workaround.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Abel Vesa 2019-08-06 18:35:23 +03:00 committed by Dong Aisheng
parent 4d3a0f7344
commit 2fe889b77c
1 changed files with 11 additions and 0 deletions
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11
drivers/irqchip/irq-imx-gpcv2.c
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@ -13,6 +13,7 @@
#include <linux/irqchip.h>
#include <linux/syscore_ops.h>
#include <linux/smp.h>
#include <linux/cpuidle.h>
#define FSL_SIP_GPC 0xC2000000
#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05
@ -96,6 +97,16 @@ static void imx_gpcv2_raise_softirq(const struct cpumask *mask,
static void imx_gpcv2_wake_request_fixup(void)
{
struct regmap *iomux_gpr;
struct arm_smccc_res res;
arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_CORE_WAKE,
0, 0, 0, 0, 0, 0, &res);
if (res.a0) {
pr_warn("irq-imx-gpcv2: EL3 does not support FSL_SIP_CONFIG_GPC_CORE_WAKE, disabling cpuidle.\n");
disable_cpuidle();
return;
}
/* hijack the already registered smp cross call handler */
__gic_v3_smp_cross_call = __smp_cross_call;