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drm/tegra: Stop CRTC at CRTC disable time 

Previously output drivers would all stop the display controller in their
disable path. However with the transition to atomic modesetting the
display controller needs to be kept running until all planes have been
disabled so that software can properly determine (using VBLANK counts)
when it is safe to remove the framebuffers associated with the planes.

Moving this code into the display controller's disable path also gets
rid of the duplication of this into all output drivers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Thierry Reding 2014-11-21 17:35:54 +01:00
parent 62b9e06321
commit 36904adf21
5 changed files with 6 additions and 16 deletions
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6
drivers/gpu/drm/tegra/dc.c
View File

@ -940,6 +940,7 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
struct tegra_dc *dc = to_tegra_dc(crtc);
struct drm_device *drm = crtc->dev;
struct drm_plane *plane;
u32 value;
drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
if (plane->crtc == crtc) {
@ -953,6 +954,11 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
}
}
/* stop the display controller */
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
drm_crtc_vblank_off(crtc);
tegra_dc_commit(dc);
}

4
drivers/gpu/drm/tegra/dsi.c
View File

@ -769,10 +769,6 @@ static int tegra_output_dsi_disable(struct tegra_output *output)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
value &= ~DSI_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

4
drivers/gpu/drm/tegra/hdmi.c
View File

@ -1033,10 +1033,6 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
*/
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
value &= ~HDMI_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

4
drivers/gpu/drm/tegra/rgb.c
View File

@ -143,10 +143,6 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
tegra_dc_commit(rgb->dc);

4
drivers/gpu/drm/tegra/sor.c
View File

@ -1071,10 +1071,6 @@ static int tegra_output_sor_disable(struct tegra_output *output)
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
*/
value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
value &= ~SOR_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);