drm/i915: Fix up cpt pixel multiplier enable sequence
Bspec for the "DPLL HDMI multiplier" field says: "Restriction : The DPLL must be enabled and stable before setting these bits. These bits must be programmed after DPLL_SEL is programmed." There is apparently no restriction on programming the DPLL_SEL register wrt the DPLL. So let's just move that up before we enable the pch dpll. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3004,15 +3004,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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/* For PCH output, training FDI link */
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dev_priv->display.fdi_link_train(crtc);
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/* XXX: pch pll's can be enabled any time before we enable the PCH
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* transcoder, and we actually should do this to not upset any PCH
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* transcoder that already use the clock when we share it.
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*
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* Note that enable_shared_dpll tries to do the right thing, but
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* get_shared_dpll unconditionally resets the pll - we need that to have
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* the right LVDS enable sequence. */
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ironlake_enable_shared_dpll(intel_crtc);
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/* We need to program the right clock selection before writing the pixel
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* mutliplier into the DPLL. */
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if (HAS_PCH_CPT(dev)) {
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u32 sel;
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@ -3026,6 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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I915_WRITE(PCH_DPLL_SEL, temp);
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}
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/* XXX: pch pll's can be enabled any time before we enable the PCH
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* transcoder, and we actually should do this to not upset any PCH
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* transcoder that already use the clock when we share it.
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*
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* Note that enable_shared_dpll tries to do the right thing, but
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* get_shared_dpll unconditionally resets the pll - we need that to have
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* the right LVDS enable sequence. */
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ironlake_enable_shared_dpll(intel_crtc);
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/* set transcoder timing, panel must allow it */
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assert_panel_unlocked(dev_priv, pipe);
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ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
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