OMAP3: Add support for DPLL3 divisor values higher than 2
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
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@ -739,9 +739,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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sdrcrate = sdrc_ick.rate;
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if (rate > clk->rate)
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sdrcrate <<= ((rate / clk->rate) - 1);
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sdrcrate <<= ((rate / clk->rate) >> 1);
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else
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sdrcrate >>= ((clk->rate / rate) - 1);
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sdrcrate >>= ((clk->rate / rate) >> 1);
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sp = omap2_sdrc_get_params(sdrcrate);
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if (!sp)
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@ -768,12 +768,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
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sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
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/* REVISIT: SRAM code doesn't support other M2 divisors yet */
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WARN_ON(new_div != 1 && new_div != 2);
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div, unlock_dll, c,
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sp->mr);
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sp->mr, rate > clk->rate);
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return 0;
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}
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@ -70,6 +70,7 @@
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = new SDRC_MR_0 register value
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* r7 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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@ -77,9 +78,10 @@ ENTRY(omap3_sram_configure_core_dpll)
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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ldr r7, [sp, #64] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2 @ if increasing SDRC clk rate,
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blne configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r7, #1 @ if increasing SDRC clk rate,
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bleq configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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@ -89,7 +91,7 @@ ENTRY(omap3_sram_configure_core_dpll)
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cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1 @ if increasing SDRC clk rate,
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cmp r7, #1 @ if increasing SDRC clk rate,
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beq return_to_sdram @ return to SDRAM code, otherwise,
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bl configure_sdrc @ reprogram SDRC regs now
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mov r12, r5
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@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll, u32 f, u32 sdrc_mr);
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u32 unlock_dll, u32 f, u32 sdrc_mr,
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u32 inc);
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/* Do not use these */
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extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll, u32 f, u32 sdrc_mr);
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u32 unlock_dll, u32 f, u32 sdrc_mr,
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u32 inc);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#endif
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@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb,
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u32 m2, u32 unlock_dll,
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u32 f, u32 sdrc_mr);
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u32 f, u32 sdrc_mr, u32 inc);
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u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
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u32 f, u32 sdrc_mr)
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u32 f, u32 sdrc_mr, u32 inc)
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{
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BUG_ON(!_omap3_sram_configure_core_dpll);
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return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
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sdrc_actim_ctrla,
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sdrc_actim_ctrlb, m2,
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unlock_dll, f, sdrc_mr);
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unlock_dll, f, sdrc_mr, inc);
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}
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/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
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