OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -36,6 +36,29 @@
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.text
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/* r4 parameters */
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#define SDRC_NO_UNLOCK_DLL 0x0
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#define SDRC_UNLOCK_DLL 0x1
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/* SDRC_DLLA_CTRL bit settings */
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#define DLLIDLE_MASK 0x4
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/* SDRC_DLLA_STATUS bit settings */
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#define LOCKSTATUS_MASK 0x4
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/* SDRC_POWER bit settings */
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#define SRFRONIDLEREQ_MASK 0x40
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#define PWDENA_MASK 0x4
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/* CM_IDLEST1_CORE bit settings */
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#define ST_SDRC_MASK 0x2
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/* CM_ICLKEN1_CORE bit settings */
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#define EN_SDRC_MASK 0x2
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/* CM_CLKSEL1_PLL bit settings */
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#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
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/*
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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* r0 = new SDRC_RFR_CTRL register contents
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@ -57,13 +80,13 @@ ENTRY(omap3_sram_configure_core_dpll)
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2 @ if increasing SDRC clk rate,
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blne configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r4, #0x1 @ set the intended DLL state
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cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
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bl configure_core_dpll @ change the DPLL3 M2 divider
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bl enable_sdrc @ take SDRC out of idle
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cmp r4, #0x1 @ wait for DLL status to change
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cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1 @ if increasing SDRC clk rate,
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@ -78,33 +101,33 @@ return_to_sdram:
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unlock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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orr r12, r12, #0x4
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orr r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #0x4
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bic r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #0x40 @ enable self refresh on idle req
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bic r12, r12, #0x4 @ clear PWDENA
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orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
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bic r12, r12, #PWDENA_MASK @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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idle_sdrc:
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2 @ check for SDRC idle
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cmp r12, #2
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and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
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cmp r12, #ST_SDRC_MASK
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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@ -112,7 +135,7 @@ configure_core_dpll:
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
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orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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bx lr
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@ -123,12 +146,12 @@ wait_clk_stable:
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enable_sdrc:
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #0x2 @ enable iclk bit for SDRC
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orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2
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and r12, r12, #ST_SDRC_MASK
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cmp r12, #0
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bne wait_sdrc_idle1
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restore_sdrc_power_val:
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@ -138,14 +161,14 @@ restore_sdrc_power_val:
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wait_dll_lock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x4
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #LOCKSTATUS_MASK
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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