OMAP3 SRAM: add more comments on the SRAM code
Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -3,13 +3,12 @@
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* (C) Copyright 2007
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* Texas Instruments Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
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* Copyright (C) 2008 Nokia Corporation
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -38,13 +37,16 @@
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.text
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/*
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* Change frequency of core dpll
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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* r0 = new SDRC_RFR_CTRL register contents
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* r1 = new SDRC_ACTIM_CTRLA register contents
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* r2 = new SDRC_ACTIM_CTRLB register contents
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* r3 = new M2 divider setting (only 1 and 2 supported right now)
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* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = SDRC_MR_0 register value
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* r6 = new SDRC_MR_0 register value
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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@ -53,22 +55,22 @@ ENTRY(omap3_sram_configure_core_dpll)
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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cmp r4, #0x1
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cmp r3, #0x2 @ if increasing SDRC clk rate,
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blne configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r4, #0x1 @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put the SDRAM in self refresh
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bl configure_core_dpll
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bl enable_sdrc
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cmp r4, #0x1
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bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
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bl configure_core_dpll @ change the DPLL3 M2 divider
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bl enable_sdrc @ take SDRC out of idle
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cmp r4, #0x1 @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1
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beq return_to_sdram
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bl configure_sdrc
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mov r12, r5 @ if slowing, wait for SDRC to stabilize
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bl wait_clk_stable
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cmp r3, #0x1 @ if increasing SDRC clk rate,
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beq return_to_sdram @ return to SDRAM code, otherwise,
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bl configure_sdrc @ reprogram SDRC regs now
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mov r12, r5
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bl wait_clk_stable @ wait for SDRC to stabilize
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return_to_sdram:
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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@ -93,6 +95,7 @@ sdram_in_selfrefresh:
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bic r12, r12, #0x4 @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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idle_sdrc:
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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