OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -771,9 +771,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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/* REVISIT: SRAM code doesn't support other M2 divisors yet */
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WARN_ON(new_div != 1 && new_div != 2);
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/* REVISIT: Add SDRC_MR changing to this code also */
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div, unlock_dll, c);
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sp->actim_ctrlb, new_div, unlock_dll, c,
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sp->mr);
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return 0;
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}
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@ -44,12 +44,14 @@
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = SDRC_MR_0 register value
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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@ -151,7 +153,9 @@ configure_sdrc:
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r2, [r11] @ posted-write barrier for SDRC
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ldr r11, omap3_sdrc_mr_0
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str r6, [r11]
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ldr r6, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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@ -168,6 +172,8 @@ omap3_sdrc_actim_ctrla:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
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omap3_sdrc_actim_ctrlb:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
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omap3_sdrc_mr_0:
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.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
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omap3_sdrc_dlla_status:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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omap3_sdrc_dlla_ctrl:
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@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll, u32 f);
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u32 unlock_dll, u32 f, u32 sdrc_mr);
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/* Do not use these */
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extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll, u32 f);
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u32 unlock_dll, u32 f, u32 sdrc_mr);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#endif
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@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb,
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u32 m2, u32 unlock_dll,
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u32 f);
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u32 f, u32 sdrc_mr);
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u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
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u32 f)
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u32 f, u32 sdrc_mr)
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{
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BUG_ON(!_omap3_sram_configure_core_dpll);
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return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
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sdrc_actim_ctrla,
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sdrc_actim_ctrlb, m2,
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unlock_dll, f);
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unlock_dll, f, sdrc_mr);
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}
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/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
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