ARM64: DT: Hisilicon SoC DT updates for 4.18v2
- Add mailbox, stub clock, CPU frequency scaling, thermal cooling management and pcie msi interruption support for hi3660 - Add LPC support for hip06 and hip07 - Add PCIe, usb and emmc support for hi3798cv200 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJa+umIAAoJEAvIV27ZiWZcItwP/R4kgy+0SKzmHzTXVdfIv1UT PrxVLLBsGfk2XosBfLAOGOIR7eVH4AtYWs1J6Nsu8yIs1df3+YdUeapOpdzGJiA3 rKG5boI4v2rrMQ75T8gXXzePAth+zgwC3JFKFZioU2kpBYLW1GM9spT7dhdb+Xj8 gETrp/I120KrtSCAmxwT0dG0n0uwDB1ZtWGTDiVFJD6A5LNJte96kd5haShMqLo1 HACVKNc5i5QqfLu/NjsNxu5KBUYUjgHbZnuqbnpfGi2mBjlLYnfp/l0Qu88nfbiO xVlWem7H0OziO5XxNNaLk8mZ9jZw+Ak9sspDa9+htM4GMkqM0z6WdN52E9Guj1Ll xOl3ZghM3Z/qwZB4Rnlduhi2R7IKi6el+942Kc3A6gyhJaifHxBn4+BMJ2t1UytR zTIEj+YhgYQ37TvR/PZkESrAXxpKtH4CwNRZ7gycWBJaVhSGsZTGEW53AnqeTAOf EKGDoQ/iyZ/T4vNArCAGa7V1Opf3P4pj60rnc8gC6AidDlys9cKEFmkOXTtdFJe0 D3DW9pVIstUm31znKSob13DRHZLPMyoui1ZjDNrbEPLp9ayY5FVkEg2c/1w/dUvo wNfpTWhgQB8mvsqiQ5P4urjyv9Gv45v4GfRB7GAAed9s7YYXzOmuOpktthQMmLl/ /Zjt36JIyhQ8g//E44NC =7lcf -----END PGP SIGNATURE----- Merge tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi into next/dt ARM64: DT: Hisilicon SoC DT updates for 4.18v2 - Add mailbox, stub clock, CPU frequency scaling, thermal cooling management and pcie msi interruption support for hi3660 - Add LPC support for hip06 and hip07 - Add PCIe, usb and emmc support for hi3798cv200 * tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi3798cv200: enable emmc support for poplar board arm64: dts: hi3798cv200: enable usb2 support for poplar board arm64: dts: hi3798cv200: enable PCIe support for poplar board arm64: dts: hisi: Enable Hisi LPC node for hip07 arm64: dts: hisi: Enable Hisi LPC node for hip06 arm64: dts: hi3660: Add pcie msi interrupt attribute arm64: dts: hi3660: Add thermal cooling management arm64: dts: hi3660: Add CPU frequency scaling support arm64: dts: hi3660: Add stub clock node arm64: dts: hi3660: Add mailbox node Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
3c13e601a2
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@ -7,6 +7,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/hi3660-clock.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "hisilicon,hi3660";
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@ -62,6 +63,10 @@
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <592>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <110>;
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};
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cpu1: cpu@1 {
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@ -72,6 +77,8 @@
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <592>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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@ -82,6 +89,8 @@
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <592>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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@ -92,6 +101,8 @@
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <592>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu4: cpu@100 {
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@ -102,6 +113,10 @@
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next-level-cache = <&A73_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
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capacity-dmips-mhz = <1024>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <550>;
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};
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cpu5: cpu@101 {
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@ -112,6 +127,8 @@
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next-level-cache = <&A73_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
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capacity-dmips-mhz = <1024>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu6: cpu@102 {
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@ -122,6 +139,8 @@
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next-level-cache = <&A73_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
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capacity-dmips-mhz = <1024>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu7: cpu@103 {
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@ -132,6 +151,8 @@
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next-level-cache = <&A73_L2>;
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
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capacity-dmips-mhz = <1024>;
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clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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idle-states {
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@ -174,6 +195,76 @@
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};
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <533000000>;
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opp-microvolt = <700000>;
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clock-latency-ns = <300000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <999000000>;
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opp-microvolt = <800000>;
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clock-latency-ns = <300000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <1402000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <300000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1709000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <300000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1844000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp10 {
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opp-hz = /bits/ 64 <903000000>;
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opp-microvolt = <700000>;
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clock-latency-ns = <300000>;
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};
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opp11 {
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opp-hz = /bits/ 64 <1421000000>;
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opp-microvolt = <800000>;
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clock-latency-ns = <300000>;
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};
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opp12 {
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opp-hz = /bits/ 64 <1805000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <300000>;
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};
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opp13 {
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opp-hz = /bits/ 64 <2112000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <300000>;
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};
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opp14 {
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opp-hz = /bits/ 64 <2362000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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};
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};
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gic: interrupt-controller@e82b0000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
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@ -274,6 +365,21 @@
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#reset-cells = <2>;
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};
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mailbox: mailbox@e896b000 {
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compatible = "hisilicon,hi3660-mbox";
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reg = <0x0 0xe896b000 0x0 0x1000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <3>;
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};
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stub_clock: stub_clock@e896b500 {
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compatible = "hisilicon,hi3660-stub-clk";
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reg = <0x0 0xe896b500 0x0 0x0100>;
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#clock-cells = <1>;
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mboxes = <&mailbox 13 3 0>;
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};
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dual_timer0: timer@fff14000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x0 0xfff14000 0x0 0x1000>;
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@ -872,6 +978,8 @@
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0x0 0x02000000>;
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num-lanes = <1>;
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#interrupt-cells = <1>;
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interrupts = <0 283 4>;
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interrupt-names = "msi";
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1
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&gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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@ -972,5 +1080,44 @@
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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#thermal-sensor-cells = <1>;
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};
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thermal-zones {
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cls0: cls0 {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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sustainable-power = <4500>;
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/* sensor ID */
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thermal-sensors = <&tsensor 1>;
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trips {
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threshold: trip-point@0 {
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temperature = <65000>;
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hysteresis = <1000>;
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type = "passive";
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};
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target: trip-point@1 {
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temperature = <75000>;
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hysteresis = <1000>;
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type = "passive";
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};
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};
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cooling-maps {
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map0 {
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trip = <&target>;
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contribution = <1024>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&target>;
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contribution = <512>;
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cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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};
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};
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@ -11,6 +11,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include "hi3798cv200.dtsi"
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#include "poplar-pinctrl.dtsi"
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/ {
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model = "HiSilicon Poplar Development Board";
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@ -61,6 +62,33 @@
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default-state = "off";
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};
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};
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reg_pcie: regulator-pcie {
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compatible = "regulator-fixed";
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regulator-name = "3V3_PCIE0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio6 7 0>;
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enable-active-high;
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};
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};
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&ehci {
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status = "okay";
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};
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&emmc {
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
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&emmc_pins_3 &emmc_pins_4>;
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fifo-depth = <256>;
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clock-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&gmac1 {
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@ -146,6 +174,16 @@
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&pcie {
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reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
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vpcie-supply = <®_pcie>;
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status = "okay";
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};
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&sd0 {
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bus-width = <4>;
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cap-sd-highspeed;
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@ -8,7 +8,9 @@
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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@ -106,6 +108,113 @@
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#reset-cells = <2>;
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};
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perictrl: peripheral-controller@8a20000 {
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compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
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"simple-mfd";
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reg = <0x8a20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8a20000 0x1000>;
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usb2_phy1: usb2-phy@120 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x120 0x4>;
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clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
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resets = <&crg 0xbc 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy1_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 8>;
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};
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usb2_phy1_port1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 9>;
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};
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};
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usb2_phy2: usb2-phy@124 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x124 0x4>;
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clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
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resets = <&crg 0xbc 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy2_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 10>;
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};
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};
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combphy0: phy@850 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x850 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY0_CLK>;
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resets = <&crg 0x188 4>;
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assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
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assigned-clock-rates = <100000000>;
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hisilicon,fixed-mode = <PHY_TYPE_USB3>;
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};
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combphy1: phy@858 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x858 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY1_CLK>;
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resets = <&crg 0x188 12>;
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assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
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assigned-clock-rates = <100000000>;
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hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
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};
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};
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pmx0: pinconf@8a21000 {
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compatible = "pinconf-single";
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reg = <0x8a21000 0x180>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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pinctrl-single,gpio-range = <
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&range 0 8 2 /* GPIO 0 */
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&range 8 1 0 /* GPIO 1 */
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&range 9 4 2
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&range 13 1 0
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&range 14 1 1
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&range 15 1 0
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&range 16 5 0 /* GPIO 2 */
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&range 21 3 1
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&range 24 4 1 /* GPIO 3 */
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&range 28 2 2
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&range 86 1 1
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&range 87 1 0
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&range 30 4 2 /* GPIO 4 */
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&range 34 3 0
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&range 37 1 2
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&range 38 3 2 /* GPIO 6 */
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&range 41 5 0
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&range 46 8 1 /* GPIO 7 */
|
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&range 54 8 1 /* GPIO 8 */
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&range 64 7 1 /* GPIO 9 */
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&range 71 1 0
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&range 72 6 1 /* GPIO 10 */
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&range 78 1 0
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&range 79 1 1
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&range 80 6 1 /* GPIO 11 */
|
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&range 70 2 1
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&range 88 8 0 /* GPIO 12 */
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>;
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range: gpio-range {
|
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#pinctrl-single,gpio-range-cells = <3>;
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};
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||||
};
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|
||||
uart0: serial@8b00000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x8b00000 0x1000>;
|
||||
|
|
@ -205,12 +314,17 @@
|
|||
};
|
||||
|
||||
emmc: mmc@9830000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
compatible = "hisilicon,hi3798cv200-dw-mshc";
|
||||
reg = <0x9830000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_MMC_CIU_CLK>,
|
||||
<&crg HISTB_MMC_BIU_CLK>;
|
||||
clock-names = "ciu", "biu";
|
||||
<&crg HISTB_MMC_BIU_CLK>,
|
||||
<&crg HISTB_MMC_SAMPLE_CLK>,
|
||||
<&crg HISTB_MMC_DRV_CLK>;
|
||||
clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
|
||||
resets = <&crg 0xa0 4>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@8b20000 {
|
||||
|
|
@ -221,6 +335,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 0 8>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -234,6 +349,13 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <
|
||||
&pmx0 0 8 1
|
||||
&pmx0 1 9 4
|
||||
&pmx0 5 13 1
|
||||
&pmx0 6 14 1
|
||||
&pmx0 7 15 1
|
||||
>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -247,6 +369,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -260,6 +383,12 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <
|
||||
&pmx0 0 24 4
|
||||
&pmx0 4 28 2
|
||||
&pmx0 6 86 1
|
||||
&pmx0 7 87 1
|
||||
>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -273,6 +402,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -299,6 +429,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -312,6 +443,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 46 8>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -325,6 +457,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 54 8>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -338,6 +471,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -351,6 +485,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -364,6 +499,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -377,6 +513,7 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pmx0 0 88 8>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
|
|
@ -419,5 +556,67 @@
|
|||
clocks = <&sysctrl HISTB_IR_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie: pcie@9860000 {
|
||||
compatible = "hisilicon,hi3798cv200-pcie";
|
||||
reg = <0x9860000 0x1000>,
|
||||
<0x0 0x2000>,
|
||||
<0x2000000 0x01000000>;
|
||||
reg-names = "control", "rc-dbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0 15>;
|
||||
num-lanes = <1>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
|
||||
0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_PCIE_AUX_CLK>,
|
||||
<&crg HISTB_PCIE_PIPE_CLK>,
|
||||
<&crg HISTB_PCIE_SYS_CLK>,
|
||||
<&crg HISTB_PCIE_BUS_CLK>;
|
||||
clock-names = "aux", "pipe", "sys", "bus";
|
||||
resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
|
||||
reset-names = "soft", "sys", "bus";
|
||||
phys = <&combphy1 PHY_TYPE_PCIE>;
|
||||
phy-names = "phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: ohci@9880000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x9880000 0x10000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_USB2_BUS_CLK>,
|
||||
<&crg HISTB_USB2_12M_CLK>,
|
||||
<&crg HISTB_USB2_48M_CLK>;
|
||||
clock-names = "bus", "clk12", "clk48";
|
||||
resets = <&crg 0xb8 12>;
|
||||
reset-names = "bus";
|
||||
phys = <&usb2_phy1_port0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci: ehci@9890000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x9890000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_USB2_BUS_CLK>,
|
||||
<&crg HISTB_USB2_PHY_CLK>,
|
||||
<&crg HISTB_USB2_UTMI_CLK>;
|
||||
clock-names = "bus", "phy", "utmi";
|
||||
resets = <&crg 0xb8 12>,
|
||||
<&crg 0xb8 16>,
|
||||
<&crg 0xb8 13>;
|
||||
reset-names = "bus", "phy", "utmi";
|
||||
phys = <&usb2_phy1_port0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,6 +25,14 @@
|
|||
chosen { };
|
||||
};
|
||||
|
||||
&ipmi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -350,6 +350,27 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
isa@a01b0000 {
|
||||
compatible = "hisilicon,hip06-lpc";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <0x0 0xa01b0000 0x0 0x1000>;
|
||||
|
||||
ipmi0: bt@e4 {
|
||||
compatible = "ipmi-bt";
|
||||
device_type = "ipmi";
|
||||
reg = <0x01 0xe4 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: lpc-uart@2f8 {
|
||||
compatible = "ns16550a";
|
||||
clock-frequency = <1843200>;
|
||||
reg = <0x01 0x2f8 0x08>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
refclk: refclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,10 @@
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
&ipmi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb_ohci {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1114,6 +1114,20 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
isa@a01b0000 {
|
||||
compatible = "hisilicon,hip07-lpc";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <0x0 0xa01b0000 0x0 0x1000>;
|
||||
|
||||
ipmi0: bt@e4 {
|
||||
compatible = "ipmi-bt";
|
||||
device_type = "ipmi";
|
||||
reg = <0x01 0xe4 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@602b0000 {
|
||||
compatible = "arm,sbsa-uart";
|
||||
reg = <0x0 0x602b0000 0x0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Pinctrl dts file for HiSilicon Poplar board
|
||||
*
|
||||
* Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/hisi.h>
|
||||
|
||||
/* value, enable bits, disable bits, mask */
|
||||
#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
|
||||
(value << 13) (enable << 13) (disable << 13) (mask << 13)
|
||||
#define PINCTRL_PULLUP(value, enable, disable, mask) \
|
||||
(value << 12) (enable << 12) (disable << 12) (mask << 12)
|
||||
#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8)
|
||||
#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
|
||||
|
||||
&pmx0 {
|
||||
emmc_pins_1: emmc-pins-1 {
|
||||
pinctrl-single,pins = <
|
||||
0x000 MUX_M2
|
||||
0x004 MUX_M2
|
||||
0x008 MUX_M2
|
||||
0x00c MUX_M2
|
||||
0x010 MUX_M2
|
||||
0x014 MUX_M2
|
||||
0x018 MUX_M2
|
||||
0x01c MUX_M2
|
||||
0x024 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(0xb, 0xf)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_2: emmc-pins-2 {
|
||||
pinctrl-single,pins = <
|
||||
0x028 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(0x9, 0xf)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_3: emmc-pins-3 {
|
||||
pinctrl-single,pins = <
|
||||
0x02c MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(3, 3)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_4: emmc-pins-4 {
|
||||
pinctrl-single,pins = <
|
||||
0x030 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(1, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(3, 3)
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue