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drm/amdgpu: check gfx pipe availability before toggling its interrupts 

GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0
are only applicable to me0 pipe0.

For ASICs that have gfx pipe removed, don't toggle
those bits.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zero-sugar-mainline-defconfig
Hawking Zhang 2020-11-21 21:58:19 +08:00 committed by Alex Deucher
parent d0f2f634f5
commit 462fbeb1fc
1 changed files with 8 additions and 1 deletions
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9
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
u32 tmp;
/* don't toggle interrupts that are only applicable
* to me0 pipe0 on AISCs that have me0 removed */
if (!adev->gfx.num_gfx_rings)
return;
tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);