drm/amdgpu: check gfx pipe availability before toggling its interrupts
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0 are only applicable to me0 pipe0. For ASICs that have gfx pipe removed, don't toggle those bits. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
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static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
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static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
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bool enable)
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bool enable)
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{
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{
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u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
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u32 tmp;
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/* don't toggle interrupts that are only applicable
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* to me0 pipe0 on AISCs that have me0 removed */
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if (!adev->gfx.num_gfx_rings)
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return;
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tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
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tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
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tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
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tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
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tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
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