dt-bindings: clock: Document S32V234 MC_CGM and MC_ME

Add DT bindings documentation for the upcoming S32V234 clk driver. Add
s32v234-clock.h header, which is referred in MC_CGM documentation.

Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>

Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt

@@ -0,0 +1,31 @@
+* NXP S32V234 Clock Generation Modules (MC_CGMs)
+
+The SoC supports four Clock Generation Modules, which provide registers for
+system and peripherals clock source selection and division. See chapters 22
+("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry
+Module (MC_ME)") in the reference manual[1].
+
+This binding uses the common clock binding:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible:
+	Should be:
+	- "fsl,s32v234-mc_cgm0" for MC_CGM_0
+	- "fsl,s32v234-mc_cgm1" for MC_CGM_1
+	- "fsl,s32v234-mc_cgm2" for MC_CGM_2
+	- "fsl,s32v234-mc_cgm3" for MC_CGM_3
+- reg:
+	Location and length of the register set
+- #clock-cells (only for MC_CGM_0):
+	Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock
+	specifiers allowed in the clocks property of consumers.
+
+Example:
+clks: mc_cgm0@4003c000 {
+	compatible = "fsl,s32v234-mc_cgm0";
+	reg = <0x0 0x4003C000 0x0 0x1000>;
+	#clock-cells = <1>;
+};
+
+[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM

Documentation/devicetree/bindings/clock/s32v234-mc_me.txt

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+* NXP S32V234 Mode Entry Module (MC_ME)
+
+See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the
+reference manual[1].
+
+Required properties:
+- compatible: Should be "fsl,s32v234-mc_me"
+- reg: Location and length of the register set
+
+Example:
+mc_me: mc_me@4004a000 {
+	compatible = "fsl,s32v234-mc_me";
+	reg = <0x0 0x4004A000 0x0 0x1000>;
+};
+
+[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM

include/dt-bindings/clock/s32v234-clock.h

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+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S32V234_H
+#define __DT_BINDINGS_CLOCK_S32V234_H
+
+#define	S32V234_CLK_DUMMY			0
+#define	S32V234_CLK_FXOSC			1
+#define	S32V234_CLK_FIRC			2
+/* PERIPH PLL */
+#define	S32V234_CLK_PERIPHPLL_SRC_SEL		3
+#define	S32V234_CLK_PERIPHPLL_VCO		4
+#define	S32V234_CLK_PERIPHPLL_PHI0		5
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV3		6
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV5		7
+#define	S32V234_CLK_PERIPHPLL_PHI1		8
+
+#define	S32V234_CLK_END				9
+#endif /* __DT_BINDINGS_CLOCK_S32V234_H */