Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
r600 dpm fixes, old school card dac fixes, lockup fixes endian fixes * 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux: drm/radeon/dpm: fix r600_enable_sclk_control() drm/radeon/dpm: implement force performance levels for rv6xx drm/radeon/dpm: fix displaygap programming on rv6xx drm/radeon/dpm: fix a typo in the rv6xx mclk setup drm/radeon: fix combios tables on older cards drm/radeon: improve dac adjust heuristics for legacy pdac drm/radeon: Another card with wrong primary dac adj drm/radeon: fix endian issues with DP handling (v3) drm/radeon/vm: only align the pt base to 32k drm/radeon: wait for 3D idle before using CP DMA
This commit is contained in:
commit
4795b95a59
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@ -44,6 +44,41 @@ static char *pre_emph_names[] = {
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};
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/***** radeon AUX functions *****/
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/* Atom needs data in little endian format
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* so swap as appropriate when copying data to
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* or from atom. Note that atom operates on
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* dw units.
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*/
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static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
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{
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#ifdef __BIG_ENDIAN
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u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
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u32 *dst32, *src32;
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int i;
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memcpy(src_tmp, src, num_bytes);
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src32 = (u32 *)src_tmp;
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dst32 = (u32 *)dst_tmp;
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if (to_le) {
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = cpu_to_le32(src32[i]);
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memcpy(dst, dst_tmp, num_bytes);
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} else {
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u8 dws = num_bytes & ~3;
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = le32_to_cpu(src32[i]);
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memcpy(dst, dst_tmp, dws);
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if (num_bytes % 4) {
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for (i = 0; i < (num_bytes % 4); i++)
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dst[dws+i] = dst_tmp[dws+i];
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}
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}
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#else
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memcpy(dst, src, num_bytes);
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#endif
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}
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union aux_channel_transaction {
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PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
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PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
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@ -65,10 +100,10 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
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base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
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memcpy(base, send, send_bytes);
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radeon_copy_swap(base, send, send_bytes, true);
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args.v1.lpAuxRequest = 0 + 4;
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args.v1.lpDataOut = 16 + 4;
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args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
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args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
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args.v1.ucDataOutLen = 0;
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args.v1.ucChannelID = chan->rec.i2c_id;
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args.v1.ucDelay = delay / 10;
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@ -102,7 +137,7 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
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recv_bytes = recv_size;
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if (recv && recv_size)
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memcpy(recv, base + 16, recv_bytes);
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radeon_copy_swap(recv, base + 16, recv_bytes, false);
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return recv_bytes;
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}
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@ -3166,7 +3166,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
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size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
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num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 6 + 21);
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r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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@ -3181,6 +3181,9 @@ int r600_copy_cpdma(struct radeon_device *rdev,
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radeon_semaphore_free(rdev, &sem, NULL);
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
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radeon_ring_write(ring, WAIT_3D_IDLE_bit);
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for (i = 0; i < num_loops; i++) {
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cur_size_in_bytes = size_in_bytes;
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if (cur_size_in_bytes > 0x1fffff)
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|
|
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@ -278,9 +278,9 @@ bool r600_dynamicpm_enabled(struct radeon_device *rdev)
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void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);
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WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
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else
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WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
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WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
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}
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void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
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|
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@ -1161,6 +1161,7 @@ static struct radeon_asic rv6xx_asic = {
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.get_mclk = &rv6xx_dpm_get_mclk,
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.print_power_state = &rv6xx_dpm_print_power_state,
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.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
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.force_performance_level = &rv6xx_dpm_force_performance_level,
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},
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.pflip = {
|
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.pre_page_flip = &rs600_pre_page_flip,
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|
|
|
@ -421,6 +421,8 @@ void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
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struct radeon_ps *ps);
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void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
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struct seq_file *m);
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int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
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enum radeon_dpm_forced_level level);
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/* rs780 dpm */
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int rs780_dpm_init(struct radeon_device *rdev);
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int rs780_dpm_enable(struct radeon_device *rdev);
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@ -147,7 +147,7 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
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enum radeon_combios_table_offset table)
|
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{
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struct radeon_device *rdev = dev->dev_private;
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int rev;
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int rev, size;
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uint16_t offset = 0, check_offset;
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if (!rdev->bios)
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|
@ -156,174 +156,106 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
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switch (table) {
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/* absolute offset tables */
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case COMBIOS_ASIC_INIT_1_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0xc);
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if (check_offset)
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offset = check_offset;
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check_offset = 0xc;
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break;
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case COMBIOS_BIOS_SUPPORT_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x14);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x14;
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break;
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case COMBIOS_DAC_PROGRAMMING_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x2a;
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break;
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case COMBIOS_MAX_COLOR_DEPTH_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x2c;
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break;
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case COMBIOS_CRTC_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x2e;
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break;
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case COMBIOS_PLL_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x30);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x30;
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break;
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case COMBIOS_TV_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x32);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x32;
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break;
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case COMBIOS_DFP_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x34);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x34;
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break;
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case COMBIOS_HW_CONFIG_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x36);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x36;
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break;
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case COMBIOS_MULTIMEDIA_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x38);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x38;
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break;
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case COMBIOS_TV_STD_PATCH_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x3e;
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break;
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case COMBIOS_LCD_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x40);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x40;
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break;
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case COMBIOS_MOBILE_INFO_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x42);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x42;
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break;
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case COMBIOS_PLL_INIT_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x46);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x46;
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break;
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case COMBIOS_MEM_CONFIG_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x48);
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if (check_offset)
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offset = check_offset;
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check_offset = 0x48;
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break;
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case COMBIOS_SAVE_MASK_TABLE:
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check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
|
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if (check_offset)
|
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offset = check_offset;
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check_offset = 0x4a;
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break;
|
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case COMBIOS_HARDCODED_EDID_TABLE:
|
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check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
|
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if (check_offset)
|
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offset = check_offset;
|
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check_offset = 0x4c;
|
||||
break;
|
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case COMBIOS_ASIC_INIT_2_TABLE:
|
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check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
|
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if (check_offset)
|
||||
offset = check_offset;
|
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check_offset = 0x4e;
|
||||
break;
|
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case COMBIOS_CONNECTOR_INFO_TABLE:
|
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check_offset = RBIOS16(rdev->bios_header_start + 0x50);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
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check_offset = 0x50;
|
||||
break;
|
||||
case COMBIOS_DYN_CLK_1_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x52);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x52;
|
||||
break;
|
||||
case COMBIOS_RESERVED_MEM_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x54);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x54;
|
||||
break;
|
||||
case COMBIOS_EXT_TMDS_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x58);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x58;
|
||||
break;
|
||||
case COMBIOS_MEM_CLK_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x5a;
|
||||
break;
|
||||
case COMBIOS_EXT_DAC_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x5c;
|
||||
break;
|
||||
case COMBIOS_MISC_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x5e;
|
||||
break;
|
||||
case COMBIOS_CRT_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x60);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x60;
|
||||
break;
|
||||
case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x62);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x62;
|
||||
break;
|
||||
case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x64);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x64;
|
||||
break;
|
||||
case COMBIOS_FAN_SPEED_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x66);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x66;
|
||||
break;
|
||||
case COMBIOS_OVERDRIVE_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x68);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x68;
|
||||
break;
|
||||
case COMBIOS_OEM_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x6a;
|
||||
break;
|
||||
case COMBIOS_DYN_CLK_2_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x6c;
|
||||
break;
|
||||
case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x6e;
|
||||
break;
|
||||
case COMBIOS_I2C_INFO_TABLE:
|
||||
check_offset = RBIOS16(rdev->bios_header_start + 0x70);
|
||||
if (check_offset)
|
||||
offset = check_offset;
|
||||
check_offset = 0x70;
|
||||
break;
|
||||
/* relative offset tables */
|
||||
case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
|
||||
|
@ -439,11 +371,16 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
|
|||
}
|
||||
break;
|
||||
default:
|
||||
check_offset = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return offset;
|
||||
size = RBIOS8(rdev->bios_header_start + 0x6);
|
||||
/* check absolute offset tables */
|
||||
if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
|
||||
offset = RBIOS16(rdev->bios_header_start + check_offset);
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
|
||||
|
@ -965,16 +902,22 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
|
|||
dac = RBIOS8(dac_info + 0x3) & 0xf;
|
||||
p_dac->ps2_pdac_adj = (bg << 8) | (dac);
|
||||
}
|
||||
/* if the values are all zeros, use the table */
|
||||
if (p_dac->ps2_pdac_adj)
|
||||
/* if the values are zeros, use the table */
|
||||
if ((dac == 0) || (bg == 0))
|
||||
found = 0;
|
||||
else
|
||||
found = 1;
|
||||
}
|
||||
|
||||
/* quirks */
|
||||
/* Radeon 9100 (R200) */
|
||||
if ((dev->pdev->device == 0x514D) &&
|
||||
/* Radeon 7000 (RV100) */
|
||||
if (((dev->pdev->device == 0x5159) &&
|
||||
(dev->pdev->subsystem_vendor == 0x174B) &&
|
||||
(dev->pdev->subsystem_device == 0x7149)) {
|
||||
(dev->pdev->subsystem_device == 0x7c28)) ||
|
||||
/* Radeon 9100 (R200) */
|
||||
((dev->pdev->device == 0x514D) &&
|
||||
(dev->pdev->subsystem_vendor == 0x174B) &&
|
||||
(dev->pdev->subsystem_device == 0x7149))) {
|
||||
/* vbios value is bad, use the default */
|
||||
found = 0;
|
||||
}
|
||||
|
|
|
@ -466,7 +466,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
|
|||
size += rdev->vm_manager.max_pfn * 8;
|
||||
size *= 2;
|
||||
r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
|
||||
RADEON_VM_PTB_ALIGN(size),
|
||||
RADEON_GPU_PAGE_ALIGN(size),
|
||||
RADEON_VM_PTB_ALIGN_SIZE,
|
||||
RADEON_GEM_DOMAIN_VRAM);
|
||||
if (r) {
|
||||
|
@ -621,7 +621,7 @@ int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm)
|
|||
}
|
||||
|
||||
retry:
|
||||
pd_size = RADEON_VM_PTB_ALIGN(radeon_vm_directory_size(rdev));
|
||||
pd_size = radeon_vm_directory_size(rdev);
|
||||
r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
|
||||
&vm->page_directory, pd_size,
|
||||
RADEON_VM_PTB_ALIGN_SIZE, false);
|
||||
|
@ -953,8 +953,8 @@ static int radeon_vm_update_pdes(struct radeon_device *rdev,
|
|||
retry:
|
||||
r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
|
||||
&vm->page_tables[pt_idx],
|
||||
RADEON_VM_PTB_ALIGN(RADEON_VM_PTE_COUNT * 8),
|
||||
RADEON_VM_PTB_ALIGN_SIZE, false);
|
||||
RADEON_VM_PTE_COUNT * 8,
|
||||
RADEON_GPU_PAGE_SIZE, false);
|
||||
|
||||
if (r == -ENOMEM) {
|
||||
r = radeon_vm_evict(rdev, vm);
|
||||
|
|
|
@ -819,7 +819,7 @@ static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
|
|||
POWERMODE1(calculate_memory_refresh_rate(rdev,
|
||||
pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
|
||||
POWERMODE2(calculate_memory_refresh_rate(rdev,
|
||||
pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
|
||||
pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
|
||||
POWERMODE3(calculate_memory_refresh_rate(rdev,
|
||||
pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
|
||||
WREG32(ARB_RFSH_RATE, arb_refresh_rate);
|
||||
|
@ -1182,10 +1182,10 @@ static void rv6xx_program_display_gap(struct radeon_device *rdev)
|
|||
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
|
||||
|
||||
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
|
||||
if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
|
||||
if (rdev->pm.dpm.new_active_crtcs & 1) {
|
||||
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
|
||||
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
|
||||
} else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
|
||||
} else if (rdev->pm.dpm.new_active_crtcs & 2) {
|
||||
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
|
||||
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
|
||||
} else {
|
||||
|
@ -1670,6 +1670,8 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
|
|||
struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
|
||||
int ret;
|
||||
|
||||
pi->restricted_levels = 0;
|
||||
|
||||
rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
|
||||
|
||||
rv6xx_clear_vc(rdev);
|
||||
|
@ -1756,6 +1758,8 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
|
|||
|
||||
rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
|
||||
|
||||
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -2085,3 +2089,34 @@ u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
|
|||
else
|
||||
return requested_state->high.mclk;
|
||||
}
|
||||
|
||||
int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
|
||||
enum radeon_dpm_forced_level level)
|
||||
{
|
||||
struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
|
||||
|
||||
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
|
||||
pi->restricted_levels = 3;
|
||||
} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
|
||||
pi->restricted_levels = 2;
|
||||
} else {
|
||||
pi->restricted_levels = 0;
|
||||
}
|
||||
|
||||
rv6xx_clear_vc(rdev);
|
||||
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
|
||||
r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
|
||||
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
|
||||
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
|
||||
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
|
||||
rv6xx_enable_medium(rdev);
|
||||
rv6xx_enable_high(rdev);
|
||||
if (pi->restricted_levels == 3)
|
||||
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
|
||||
rv6xx_program_vc(rdev);
|
||||
rv6xx_program_at(rdev);
|
||||
|
||||
rdev->pm.dpm.forced_level = level;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue