gpio: ath79: Convert to the state container design pattern
Turn the ath79 driver into a true driver supporting multiple instances. While at it also removed unneed includes and make use of the BIT() macro. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Alban Bedel
Linus Walleij
parent
9f35382803
commit
49a5bd880c
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@ -12,61 +12,51 @@
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/gpio.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_data/gpio-ath79.h>
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#include <linux/of_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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static void __iomem *ath79_gpio_base;
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static u32 ath79_gpio_count;
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static DEFINE_SPINLOCK(ath79_gpio_lock);
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struct ath79_gpio_ctrl {
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struct gpio_chip chip;
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void __iomem *base;
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spinlock_t lock;
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};
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static void __ath79_gpio_set_value(unsigned gpio, int value)
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{
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void __iomem *base = ath79_gpio_base;
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if (value)
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
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}
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static int __ath79_gpio_get_value(unsigned gpio)
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{
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return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
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}
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static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return __ath79_gpio_get_value(offset);
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}
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#define to_ath79_gpio_ctrl(c) container_of(c, struct ath79_gpio_ctrl, chip)
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static void ath79_gpio_set_value(struct gpio_chip *chip,
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unsigned offset, int value)
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unsigned gpio, int value)
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{
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__ath79_gpio_set_value(offset, value);
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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if (value)
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__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
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}
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static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
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}
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static int ath79_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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void __iomem *base = ath79_gpio_base;
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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spin_lock_irqsave(&ctrl->lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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__raw_writel(
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__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
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ctrl->base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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@ -74,35 +64,37 @@ static int ath79_gpio_direction_input(struct gpio_chip *chip,
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static int ath79_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = ath79_gpio_base;
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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spin_lock_irqsave(&ctrl->lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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__raw_writel(
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__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
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ctrl->base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *base = ath79_gpio_base;
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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spin_lock_irqsave(&ctrl->lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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__raw_writel(
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__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
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ctrl->base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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@ -110,25 +102,26 @@ static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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void __iomem *base = ath79_gpio_base;
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struct ath79_gpio_ctrl *ctrl = to_ath79_gpio_ctrl(chip);
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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spin_lock_irqsave(&ctrl->lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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__raw_writel(
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__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & BIT(offset),
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ctrl->base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static struct gpio_chip ath79_gpio_chip = {
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static const struct gpio_chip ath79_gpio_chip = {
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.label = "ath79",
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.get = ath79_gpio_get_value,
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.set = ath79_gpio_set_value,
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@ -147,10 +140,16 @@ static int ath79_gpio_probe(struct platform_device *pdev)
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{
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struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
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struct device_node *np = pdev->dev.of_node;
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struct ath79_gpio_ctrl *ctrl;
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struct resource *res;
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u32 ath79_gpio_count;
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bool oe_inverted;
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int err;
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ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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if (np) {
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err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
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if (err) {
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@ -171,19 +170,21 @@ static int ath79_gpio_probe(struct platform_device *pdev)
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ath79_gpio_base = devm_ioremap_nocache(
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ctrl->base = devm_ioremap_nocache(
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&pdev->dev, res->start, resource_size(res));
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if (!ath79_gpio_base)
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if (!ctrl->base)
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return -ENOMEM;
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ath79_gpio_chip.dev = &pdev->dev;
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ath79_gpio_chip.ngpio = ath79_gpio_count;
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spin_lock_init(&ctrl->lock);
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memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
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ctrl->chip.dev = &pdev->dev;
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ctrl->chip.ngpio = ath79_gpio_count;
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if (oe_inverted) {
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ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
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ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
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ctrl->chip.direction_input = ar934x_gpio_direction_input;
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ctrl->chip.direction_output = ar934x_gpio_direction_output;
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}
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err = gpiochip_add(&ath79_gpio_chip);
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err = gpiochip_add(&ctrl->chip);
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if (err) {
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dev_err(&pdev->dev,
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"cannot add AR71xx GPIO chip, error=%d", err);
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