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arm64: dts: imx8qm/imx8qxp: Add GPU devices for 8QM/8QXP 

Add gpu in device tree:
arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi
arm64/boot/dts/freescale/imx8qm-mek.dts
arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi
arm64/boot/dts/freescale/imx8qm.dtsi
arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi
arm64/boot/dts/freescale/imx8qxp.dtsi

Signed-off-by: Minjie Zhuang <minjie.zhuang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Minjie Zhuang 2019-09-06 16:32:27 +08:00 committed by Dong Aisheng
parent 596b29d461
commit 4cefbf217d
7 changed files with 87 additions and 10 deletions
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14
arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
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@ -6,11 +6,13 @@
#include <dt-bindings/firmware/imx/rsrc.h>
gpu_subsys: bus@53100000 {
gpu0_subsys: bus@53100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x53100000 0x0 0x53100000 0x40000>;
ranges = <0x53100000 0x0 0x53100000 0x40000>,
<0x80000000 0x0 0x80000000 0x80000000>,
<0x0 0x0 0x0 0x10000000>;
gpu_3d0: gpu@53100000 {
compatible = "fsl,imx8-gpu";
@ -25,12 +27,4 @@ gpu_subsys: bus@53100000 {
power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
status = "disabled";
};
imx8_gpu_ss: imx8_gpu_ss {
compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
cores = <&gpu_3d0>;
reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
reg-names = "phys_baseaddr", "contiguous_mem";
status = "disabled";
};
};

31
arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi 100644
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
gpu1_subsys: bus@54100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54100000 0x0 0x54100000 0x40000>,
<0x80000000 0x0 0x80000000 0x80000000>,
<0x0 0x0 0x0 0x10000000>;
gpu_3d1: gpu@54100000 {
compatible = "fsl,imx8-gpu";
reg = <0x54100000 0x40000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>;
clock-names = "core", "shader";
assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>;
assigned-clock-rates = <800000000>, <1000000000>;
fsl,sc_gpu_pid = <IMX_SC_R_GPU_1_PID0>;
power-domains = <&pd IMX_SC_R_GPU_1_PID0>;
status = "disabled";
};
};

12
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
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@ -1206,6 +1206,18 @@
};
};
&gpu_3d0{
status = "okay";
};
&gpu_3d1{
status = "okay";
};
&imx8_gpu_ss {
status = "okay";
};
&mu_m0{
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
};

21
arch/arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi 100644
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&gpu_3d0 {
assigned-clock-rates = <800000000>, <1000000000>;
fsl,sc_gpu_pid = <IMX_SC_R_GPU_0_PID0>;
};
&gpu1_subsys {
imx8_gpu_ss: imx8_gpu1_ss {
compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss";
cores = <&gpu_3d0>, <&gpu_3d1>;
reg = <0x80000000 0x80000000>, <0x0 0x10000000>;
reg-names = "phys_baseaddr", "contiguous_mem";
depth-compression = <0>;
status = "disabled";
};
};

3
arch/arm64/boot/dts/freescale/imx8qm.dtsi
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@ -447,6 +447,8 @@
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dc0.dtsi"
#include "imx8-ss-dc1.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-gpu1.dtsi"
#include "imx8-ss-vpu.dtsi"
};
@ -460,3 +462,4 @@
#include "imx8qm-ss-lvds.dtsi"
#include "imx8qm-ss-hdmi.dtsi"
#include "imx8qm-ss-img.dtsi"
#include "imx8qm-ss-gpu.dtsi"

15
arch/arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi 100644
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&gpu0_subsys {
imx8_gpu_ss: imx8_gpu0_ss {
compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
cores = <&gpu_3d0>;
reg = <0x80000000 0x80000000>, <0x0 0x10000000>;
reg-names = "phys_baseaddr", "contiguous_mem";
status = "disabled";
};
};

1
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
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@ -321,6 +321,7 @@
#include "imx8qxp-ss-img.dtsi"
#include "imx8qxp-ss-dc.dtsi"
#include "imx8qxp-ss-lvds.dtsi"
#include "imx8qxp-ss-gpu.dtsi"
&edma2 {
status = "okay";