drm/amd/powerplay: update process pptables
Add functionality to fetch gpio table from vbios. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
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4eeed17e71
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4dc1a2d928
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@ -728,6 +728,32 @@ static int get_mm_clock_voltage_table(
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return 0;
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return 0;
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}
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}
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static int get_gpio_table(struct pp_hwmgr *hwmgr,
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struct phm_ppt_v1_gpio_table **pp_tonga_gpio_table,
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const ATOM_Tonga_GPIO_Table *atom_gpio_table)
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{
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uint32_t table_size;
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struct phm_ppt_v1_gpio_table *pp_gpio_table;
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struct phm_ppt_v1_information *pp_table_information =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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table_size = sizeof(struct phm_ppt_v1_gpio_table);
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pp_gpio_table = kzalloc(table_size, GFP_KERNEL);
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if (!pp_gpio_table)
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return -ENOMEM;
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if (pp_table_information->vdd_dep_on_sclk->count <
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atom_gpio_table->ucVRHotTriggeredSclkDpmIndex)
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PP_ASSERT_WITH_CODE(false,
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"SCLK DPM index for VRHot cannot exceed the total sclk level count!",);
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else
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pp_gpio_table->vrhot_triggered_sclk_dpm_index =
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atom_gpio_table->ucVRHotTriggeredSclkDpmIndex;
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*pp_tonga_gpio_table = pp_gpio_table;
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return 0;
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}
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/**
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/**
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* Private Function used during initialization.
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* Private Function used during initialization.
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* Initialize clock voltage dependency
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* Initialize clock voltage dependency
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@ -761,11 +787,15 @@ static int init_clock_voltage_dependency(
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const PPTable_Generic_SubTable_Header *pcie_table =
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const PPTable_Generic_SubTable_Header *pcie_table =
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(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
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(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
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le16_to_cpu(powerplay_table->usPCIETableOffset));
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le16_to_cpu(powerplay_table->usPCIETableOffset));
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const ATOM_Tonga_GPIO_Table *gpio_table =
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(const ATOM_Tonga_GPIO_Table *)(((unsigned long) powerplay_table) +
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le16_to_cpu(powerplay_table->usGPIOTableOffset));
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pp_table_information->vdd_dep_on_sclk = NULL;
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pp_table_information->vdd_dep_on_sclk = NULL;
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pp_table_information->vdd_dep_on_mclk = NULL;
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pp_table_information->vdd_dep_on_mclk = NULL;
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pp_table_information->mm_dep_table = NULL;
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pp_table_information->mm_dep_table = NULL;
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pp_table_information->pcie_table = NULL;
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pp_table_information->pcie_table = NULL;
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pp_table_information->gpio_table = NULL;
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if (powerplay_table->usMMDependencyTableOffset != 0)
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if (powerplay_table->usMMDependencyTableOffset != 0)
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result = get_mm_clock_voltage_table(hwmgr,
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result = get_mm_clock_voltage_table(hwmgr,
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@ -810,6 +840,10 @@ static int init_clock_voltage_dependency(
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result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
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result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
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pp_table_information->vdd_dep_on_sclk);
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pp_table_information->vdd_dep_on_sclk);
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if (!result && gpio_table)
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result = get_gpio_table(hwmgr, &pp_table_information->gpio_table,
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gpio_table);
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return result;
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return result;
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}
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}
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@ -1116,6 +1150,9 @@ static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
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kfree(pp_table_information->pcie_table);
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kfree(pp_table_information->pcie_table);
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pp_table_information->pcie_table = NULL;
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pp_table_information->pcie_table = NULL;
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kfree(pp_table_information->gpio_table);
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pp_table_information->gpio_table = NULL;
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kfree(hwmgr->pptable);
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kfree(hwmgr->pptable);
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hwmgr->pptable = NULL;
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hwmgr->pptable = NULL;
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