drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option
Just enable it always. This was leftover from feature bring up. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
Alex Deucher
parent
b646c1dc83
commit
5099114ba3
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@ -9,16 +9,6 @@ config DRM_AMD_DC
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support for AMDGPU. This adds required support for Vega and
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Raven ASICs.
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config DRM_AMD_DC_FBC
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bool "AMD FBC - Enable Frame Buffer Compression"
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depends on DRM_AMD_DC
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help
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Choose this option if you want to use frame buffer compression
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support.
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This is a power optimisation feature, check its availability
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on your hardware before enabling this option.
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config DRM_AMD_DC_DCN1_0
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bool "DCN 1.0 Raven family"
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depends on DRM_AMD_DC && X86
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@ -347,7 +347,6 @@ static void hotplug_notify_work_func(struct work_struct *work)
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drm_kms_helper_hotplug_event(dev);
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}
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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/* Allocate memory for FBC compressed data */
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static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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{
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@ -388,7 +387,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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}
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}
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#endif
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/* Init display KMS
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@ -3429,9 +3427,8 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
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amdgpu_dm_connector_ddc_get_modes(connector, edid);
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amdgpu_dm_connector_add_common_modes(encoder, connector);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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amdgpu_dm_fbc_init(connector);
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#endif
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return amdgpu_dm_connector->num_modes;
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}
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@ -72,13 +72,11 @@ struct irq_list_head {
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struct work_struct work;
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};
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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struct dm_comressor_info {
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void *cpu_addr;
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struct amdgpu_bo *bo_ptr;
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uint64_t gpu_addr;
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};
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#endif
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struct amdgpu_display_manager {
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@ -129,9 +127,8 @@ struct amdgpu_display_manager {
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* Caches device atomic state for suspend/resume
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*/
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struct drm_atomic_state *cached_state;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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struct dm_comressor_info compressor;
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#endif
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};
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struct amdgpu_dm_connector {
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@ -289,9 +289,7 @@ struct dc {
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bool apply_edp_fast_boot_optimization;
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/* FBC compressor */
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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struct compressor *fbc_compressor;
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#endif
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};
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enum frame_buffer_mode {
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@ -92,9 +92,7 @@ struct dc_context {
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bool created_bios;
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struct gpio_service *gpio_service;
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struct i2caux *i2caux;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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uint64_t fbc_gpu_addr;
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#endif
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};
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@ -551,9 +551,7 @@ void dce110_compressor_construct(struct dce110_compressor *compressor,
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compressor->base.lpt_channels_num = 0;
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compressor->base.attached_inst = 0;
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compressor->base.is_enabled = false;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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compressor->base.funcs = &dce110_compressor_funcs;
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#endif
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}
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@ -34,9 +34,7 @@
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#include "dce/dce_hwseq.h"
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#include "gpio_service_interface.h"
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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#include "dce110_compressor.h"
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#endif
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#include "bios/bios_parser_helper.h"
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#include "timing_generator.h"
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@ -1497,10 +1495,8 @@ static void power_down_all_hw_blocks(struct dc *dc)
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power_down_clock_sources(dc);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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#endif
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}
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static void disable_vga_and_power_gate_all_controllers(
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@ -1742,9 +1738,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
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if (events->force_trigger)
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value |= 0x1;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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value |= 0x84;
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#endif
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for (i = 0; i < num_pipes; i++)
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pipe_ctx[i]->stream_res.tg->funcs->
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@ -1872,8 +1866,6 @@ static void apply_min_clocks(
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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/*
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* Check if FBC can be enabled
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*/
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@ -1952,7 +1944,6 @@ static void enable_fbc(struct dc *dc,
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compr->funcs->enable_fbc(compr, ¶ms);
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}
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}
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#endif
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static void dce110_reset_hw_ctx_wrap(
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struct dc *dc,
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@ -2129,10 +2120,9 @@ enum dc_status dce110_apply_ctx_to_hw(
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set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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#endif
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/*TODO: when pplib works*/
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apply_min_clocks(dc, context, &clocks_state, true);
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@ -2210,12 +2200,9 @@ enum dc_status dce110_apply_ctx_to_hw(
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dcb->funcs->set_scratch_critical_state(dcb, false);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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enable_fbc(dc, context);
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#endif
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return DC_OK;
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}
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@ -2530,10 +2517,9 @@ static void init_hw(struct dc *dc)
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abm->funcs->init_backlight(abm);
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abm->funcs->abm_init(abm);
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}
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
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#endif
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}
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@ -2719,9 +2705,7 @@ static void dce110_program_front_end_for_pipe(
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struct dc_plane_state *plane_state = pipe_ctx->plane_state;
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struct xfm_grph_csc_adjustment adjust;
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struct out_csc_color_matrix tbl_entry;
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
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#endif
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unsigned int i;
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DC_LOGGER_INIT();
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memset(&tbl_entry, 0, sizeof(tbl_entry));
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@ -2762,7 +2746,6 @@ static void dce110_program_front_end_for_pipe(
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program_scaler(dc, pipe_ctx);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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/* fbc not applicable on Underlay pipe */
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if (dc->fbc_compressor && old_pipe->stream &&
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pipe_ctx->pipe_idx != underlay_idx) {
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@ -2771,7 +2754,6 @@ static void dce110_program_front_end_for_pipe(
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else
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enable_fbc(dc, dc->current_state);
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}
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#endif
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mi->funcs->mem_input_program_surface_config(
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mi,
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@ -54,9 +54,8 @@
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#define DC_LOGGER \
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dc->ctx->logger
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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#include "dce110/dce110_compressor.h"
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#endif
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#include "reg_helper.h"
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@ -1267,12 +1266,8 @@ static bool construct(
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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dc->fbc_compressor = dce110_compressor_create(ctx);
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#endif
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if (!underlay_create(ctx, &pool->base))
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goto res_create_fail;
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