drm/nouveau/clk/gm20b: add basic driver
Add a basic clock driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -121,4 +121,5 @@ int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
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int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
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int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
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int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
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int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
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#endif
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@ -2083,6 +2083,7 @@ nv12b_chipset = {
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.name = "GM20B",
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.bar = gk20a_bar_new,
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.bus = gf100_bus_new,
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.clk = gm20b_clk_new,
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.fb = gk20a_fb_new,
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.fuse = gm107_fuse_new,
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.ibus = gk20a_ibus_new,
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@ -8,6 +8,7 @@ nvkm-y += nvkm/subdev/clk/mcp77.o
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nvkm-y += nvkm/subdev/clk/gf100.o
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nvkm-y += nvkm/subdev/clk/gk104.o
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nvkm-y += nvkm/subdev/clk/gk20a.o
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nvkm-y += nvkm/subdev/clk/gm20b.o
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nvkm-y += nvkm/subdev/clk/pllnv04.o
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nvkm-y += nvkm/subdev/clk/pllgt215.o
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198
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
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198
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
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@ -0,0 +1,198 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <subdev/clk.h>
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#include <core/device.h>
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#include "priv.h"
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#include "gk20a.h"
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#define KHZ (1000)
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#define MHZ (KHZ * 1000)
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#define MASK(w) ((1 << w) - 1)
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#define BYPASSCTRL_SYS (SYS_GPCPLL_CFG_BASE + 0x340)
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#define BYPASSCTRL_SYS_GPCPLL_SHIFT 0
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#define BYPASSCTRL_SYS_GPCPLL_WIDTH 1
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static u32 pl_to_div(u32 pl)
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{
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return pl;
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}
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static u32 div_to_pl(u32 div)
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{
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return div;
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}
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static const struct gk20a_clk_pllg_params gm20b_pllg_params = {
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.min_vco = 1300000, .max_vco = 2600000,
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.min_u = 12000, .max_u = 38400,
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.min_m = 1, .max_m = 255,
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.min_n = 8, .max_n = 255,
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.min_pl = 1, .max_pl = 31,
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};
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static struct nvkm_pstate
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gm20b_pstates[] = {
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{
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.base = {
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.domain[nv_clk_src_gpc] = 76800,
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.voltage = 0,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 153600,
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.voltage = 1,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 230400,
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.voltage = 2,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 307200,
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.voltage = 3,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 384000,
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.voltage = 4,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 460800,
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.voltage = 5,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 537600,
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.voltage = 6,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 614400,
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.voltage = 7,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 691200,
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.voltage = 8,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 768000,
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.voltage = 9,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 844800,
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.voltage = 10,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 921600,
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.voltage = 11,
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},
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},
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{
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.base = {
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.domain[nv_clk_src_gpc] = 998400,
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.voltage = 12,
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},
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},
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};
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static int
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gm20b_clk_init(struct nvkm_clk *base)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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int ret;
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/* Set the global bypass control to VCO */
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nvkm_mask(device, BYPASSCTRL_SYS,
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MASK(BYPASSCTRL_SYS_GPCPLL_WIDTH) << BYPASSCTRL_SYS_GPCPLL_SHIFT,
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0);
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/* Start with lowest frequency */
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base->func->calc(base, &base->func->pstates[0].base);
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ret = base->func->prog(&clk->base);
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if (ret) {
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nvkm_error(subdev, "cannot initialize clock\n");
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return ret;
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}
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return 0;
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}
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static const struct nvkm_clk_func
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gm20b_clk_speedo0 = {
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.init = gm20b_clk_init,
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.fini = gk20a_clk_fini,
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.read = gk20a_clk_read,
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.calc = gk20a_clk_calc,
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.prog = gk20a_clk_prog,
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.tidy = gk20a_clk_tidy,
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.pstates = gm20b_pstates,
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.nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
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.domains = {
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{ nv_clk_src_crystal, 0xff },
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{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
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{ nv_clk_src_max },
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},
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};
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int
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gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
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{
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struct gk20a_clk *clk;
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int ret;
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clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return -ENOMEM;
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*pclk = &clk->base;
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ret = _gk20a_clk_ctor(device, index, &gm20b_clk_speedo0,
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&gm20b_pllg_params, clk);
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clk->pl_to_div = pl_to_div;
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clk->div_to_pl = div_to_pl;
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return ret;
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}
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