Qualcomm Device Tree Changes for v4.20
* Fix IRQ constants usage on MSM8974 * Add led, gpio-button, sdcc, and pcie nodes for IPQ8064 * Move/cleanup common nodes for IPQ8064 * Add i2c sensor nodes for MSM8974 Hammerhead * Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019 * Update coresight bindings -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbsROJAAoJEFKiBbHx2RXVgeoQAME0KidGF3FQsr/IjUD423bz lUQIXwpuHFz9D/MHqfyvZTfX9unqCV5fn8hPH86Q3ozUqZTRR9fVruVwKRgi4nkp T6fZsyB4KZrvENyHrcs9Pn1j3yKSGKTu8OcZOvOzTDotFAhy+YE9emzY+8WNFnDU CfGpghwMj3DsuTEhk/C+N/MWMMrKITNMzxVK7f7LALr9LCzrxNITu5+hZmD8bJDT P31/XnVoh3FXpue6AkYFRa8KT5VlFy4kOCMh/Uouhk2ONlPptASV1rnuZSYyfAHg NhtBYQMMyi/6dsoj3JDMz2p3HmIjZPPxbWoM98jqGPcDDOeEsvR1DCQGVM0C85x+ DWM3TBo5J0EocPzBfr4MHKcbZkOxm7xyWDKPnZfWLFu5KxgcytYbQXQPTJH1zheL khZA0ghoZ6enH+k17knPgHNxgEfFe2sZJg6FW88kMwNZyEZ3OPoIndXqjdwshc4a jEhMdiTrlM8X7IEqBS0akErVYi0uDxcD3K7IqavEjWn3GwTcw3TDNdp1ViIC7ldS Q6n9cK4V+aQ2h2gFMgKMijqbZ87Dhi2u9D1ltwxhaXDlMFTufDo+8sFD0tM9g0O6 0XlYKxBogXavL9f/23gUm2pyBjITVpRpeRlbyQh0KU24IFz9Y2BWYqBwnqBLK1D+ XwWKeLlV9b7ZJP5NvtIp =74RU -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.20 * Fix IRQ constants usage on MSM8974 * Add led, gpio-button, sdcc, and pcie nodes for IPQ8064 * Move/cleanup common nodes for IPQ8064 * Add i2c sensor nodes for MSM8974 Hammerhead * Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019 * Update coresight bindings * tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: Update coresight bindings for hardware ports ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsi ARM: dts: qcom: ipq4019: fix PCI range ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg value ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximity ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515 ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boards ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi ARM: dts: qcom: Add sdcc nodes for ipq8064 ARM: dts: qcom: Add pcie nodes for ipq8064 ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGH ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISING ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPI ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPI Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
55dc97235b
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|
@ -1611,10 +1611,11 @@
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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port {
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etb_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out0>;
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in-ports {
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port {
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etb_in: endpoint {
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remote-endpoint = <&replicator_out0>;
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};
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};
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};
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};
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@ -1626,10 +1627,11 @@
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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port {
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out1>;
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in-ports {
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port {
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tpiu_in: endpoint {
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remote-endpoint = <&replicator_out1>;
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};
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};
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};
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};
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@ -1640,7 +1642,7 @@
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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ports {
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1656,10 +1658,11 @@
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remote-endpoint = <&tpiu_in>;
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};
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};
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port@2 {
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reg = <0>;
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};
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in-ports {
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port {
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint = <&funnel_out>;
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};
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};
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@ -1673,7 +1676,7 @@
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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ports {
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1687,33 +1690,31 @@
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port@0 {
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reg = <0>;
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funnel_in0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out>;
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};
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};
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port@1 {
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reg = <1>;
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funnel_in1: endpoint {
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slave-mode;
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remote-endpoint = <&etm1_out>;
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};
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};
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port@4 {
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reg = <4>;
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funnel_in4: endpoint {
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slave-mode;
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remote-endpoint = <&etm2_out>;
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};
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};
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port@5 {
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reg = <5>;
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funnel_in5: endpoint {
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slave-mode;
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remote-endpoint = <&etm3_out>;
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};
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};
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port@8 {
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reg = <0>;
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};
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out-ports {
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port {
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funnel_out: endpoint {
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remote-endpoint = <&replicator_in>;
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};
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@ -1730,9 +1731,11 @@
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cpu = <&CPU0>;
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port {
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etm0_out: endpoint {
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remote-endpoint = <&funnel_in0>;
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out-ports {
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port {
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etm0_out: endpoint {
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remote-endpoint = <&funnel_in0>;
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};
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};
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};
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};
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@ -1746,9 +1749,11 @@
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cpu = <&CPU1>;
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port {
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etm1_out: endpoint {
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remote-endpoint = <&funnel_in1>;
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out-ports {
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port {
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etm1_out: endpoint {
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remote-endpoint = <&funnel_in1>;
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};
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};
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};
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};
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@ -1762,9 +1767,11 @@
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cpu = <&CPU2>;
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port {
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etm2_out: endpoint {
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remote-endpoint = <&funnel_in4>;
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out-ports {
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port {
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etm2_out: endpoint {
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remote-endpoint = <&funnel_in4>;
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};
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};
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};
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};
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@ -1778,9 +1785,11 @@
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cpu = <&CPU3>;
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port {
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etm3_out: endpoint {
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remote-endpoint = <&funnel_in5>;
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out-ports {
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port {
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etm3_out: endpoint {
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remote-endpoint = <&funnel_in5>;
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};
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};
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};
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};
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@ -52,78 +52,85 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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716000 1100000
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>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-48000000 {
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opp-hz = /bits/ 64 <48000000>;
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clock-latency-ns = <256000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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clock-latency-ns = <256000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <256000>;
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};
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opp-716000000 {
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opp-hz = /bits/ 64 <716000000>;
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clock-latency-ns = <256000>;
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};
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};
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pmu {
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@ -291,49 +298,49 @@
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status = "disabled";
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};
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acc0: clock-controller@b088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc0: clock-controller@b088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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};
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saw1: regulator@b099000 {
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compatible = "qcom,saw2";
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reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw1: regulator@b099000 {
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compatible = "qcom,saw2";
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reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw2: regulator@b0a9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw2: regulator@b0a9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw3: regulator@b0b9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw3: regulator@b0b9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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||||
};
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||||
|
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blsp1_uart1: serial@78af000 {
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||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
|
|
@ -387,7 +394,7 @@
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#size-cells = <2>;
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ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
|
||||
0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
|
||||
0x82000000 0 0x40300000 0x40300000 0 0x400000>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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||||
interrupt-names = "msi";
|
||||
|
|
|
|||
|
|
@ -2,26 +2,8 @@
|
|||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8064/AP148";
|
||||
compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
|
||||
compatible = "qcom,ipq8064-ap148";
|
||||
|
||||
soc {
|
||||
pinmux@800000 {
|
||||
|
|
@ -31,73 +13,22 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
buttons_pins: buttons_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
pins = "gpio54", "gpio65";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
serial@16340000 {
|
||||
i2c@16380000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
i2c4: i2c@16380000 {
|
||||
status = "ok";
|
||||
|
||||
clock-frequency = <200000>;
|
||||
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "scratch";
|
||||
reg = <0x1000000 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
ports-implemented = <0x1>;
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,2 +1,127 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include "qcom-ipq8064.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
gsbi@16300000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "ok";
|
||||
|
||||
serial@16340000 {
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "ok";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "ok";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "scratch";
|
||||
reg = <0x1000000 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata-phy@1b400000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
sata@29000000 {
|
||||
ports-implemented = <0x1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&buttons_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button@1 {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
button@2 {
|
||||
label = "wps";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led@7 {
|
||||
label = "led_usb1";
|
||||
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "usbdev";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@8 {
|
||||
label = "led_usb3";
|
||||
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "usbdev";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@9 {
|
||||
label = "status_led_fail";
|
||||
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@26 {
|
||||
label = "sata_led";
|
||||
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@53 {
|
||||
label = "status_led_pass";
|
||||
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,8 +2,11 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
|
|
@ -114,6 +117,61 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pcie0_pins: pcie0_pinmux {
|
||||
mux {
|
||||
pins = "gpio3";
|
||||
function = "pcie1_rst";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_pins: pcie1_pinmux {
|
||||
mux {
|
||||
pins = "gpio48";
|
||||
function = "pcie2_rst";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_pins: pcie2_pinmux {
|
||||
mux {
|
||||
pins = "gpio63";
|
||||
function = "pcie3_rst";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
||||
leds_pins: leds_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9",
|
||||
"gpio26", "gpio53";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
buttons_pins: buttons_pins {
|
||||
mux {
|
||||
pins = "gpio54";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
|
|
@ -373,5 +431,233 @@
|
|||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b500000 0x1000
|
||||
0x1b502000 0x80
|
||||
0x1b600000 0x100
|
||||
0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
|
||||
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc PCIE_A_CLK>,
|
||||
<&gcc PCIE_H_CLK>,
|
||||
<&gcc PCIE_PHY_CLK>,
|
||||
<&gcc PCIE_AUX_CLK>,
|
||||
<&gcc PCIE_ALT_REF_CLK>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
|
||||
assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
resets = <&gcc PCIE_ACLK_RESET>,
|
||||
<&gcc PCIE_HCLK_RESET>,
|
||||
<&gcc PCIE_POR_RESET>,
|
||||
<&gcc PCIE_PCI_RESET>,
|
||||
<&gcc PCIE_PHY_RESET>,
|
||||
<&gcc PCIE_EXT_RESET>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "disabled";
|
||||
perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b700000 0x1000
|
||||
0x1b702000 0x80
|
||||
0x1b800000 0x100
|
||||
0x31f00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
|
||||
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc PCIE_1_A_CLK>,
|
||||
<&gcc PCIE_1_H_CLK>,
|
||||
<&gcc PCIE_1_PHY_CLK>,
|
||||
<&gcc PCIE_1_AUX_CLK>,
|
||||
<&gcc PCIE_1_ALT_REF_CLK>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
|
||||
assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
resets = <&gcc PCIE_1_ACLK_RESET>,
|
||||
<&gcc PCIE_1_HCLK_RESET>,
|
||||
<&gcc PCIE_1_POR_RESET>,
|
||||
<&gcc PCIE_1_PCI_RESET>,
|
||||
<&gcc PCIE_1_PHY_RESET>,
|
||||
<&gcc PCIE_1_EXT_RESET>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "disabled";
|
||||
perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
pcie2: pci@1b900000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b900000 0x1000
|
||||
0x1b902000 0x80
|
||||
0x1ba00000 0x100
|
||||
0x35f00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
|
||||
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc PCIE_2_A_CLK>,
|
||||
<&gcc PCIE_2_H_CLK>,
|
||||
<&gcc PCIE_2_PHY_CLK>,
|
||||
<&gcc PCIE_2_AUX_CLK>,
|
||||
<&gcc PCIE_2_ALT_REF_CLK>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
|
||||
assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
resets = <&gcc PCIE_2_ACLK_RESET>,
|
||||
<&gcc PCIE_2_HCLK_RESET>,
|
||||
<&gcc PCIE_2_POR_RESET>,
|
||||
<&gcc PCIE_2_PCI_RESET>,
|
||||
<&gcc PCIE_2_PHY_RESET>,
|
||||
<&gcc PCIE_2_EXT_RESET>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
pinctrl-0 = <&pcie2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "disabled";
|
||||
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SDCC Power";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdcc1bam:dma@12402000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12402000 0x8000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC1_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
sdcc3bam:dma@12182000 {
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12182000 0x8000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC3_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
sdcc@12400000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
reg = <0x12400000 0x2000>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
max-frequency = <96000000>;
|
||||
non-removable;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sdcc@12180000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
status = "disabled";
|
||||
reg = <0x12180000 0x2000>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <192000000>;
|
||||
#mmc-ddr-1_8v;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
vqmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -241,6 +241,33 @@
|
|||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
mux {
|
||||
pins = "gpio10", "gpio11";
|
||||
function = "blsp_i2c3";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c12_pins: i2c12 {
|
||||
mux {
|
||||
pins = "gpio87", "gpio88";
|
||||
function = "blsp_i2c12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
mpu6515_pin: mpu6515 {
|
||||
irq {
|
||||
pins = "gpio73";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@f9824900 {
|
||||
|
|
@ -277,6 +304,62 @@
|
|||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@f9968000 {
|
||||
status = "ok";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c12_pins>;
|
||||
clock-frequency = <100000>;
|
||||
qcom,src-freq = <50000000>;
|
||||
|
||||
mpu6515@68 {
|
||||
compatible = "invensense,mpu6515";
|
||||
reg = <0x68>;
|
||||
interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>;
|
||||
vddio-supply = <&pm8941_lvs1>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mpu6515_pin>;
|
||||
|
||||
i2c-gate {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ak8963@f {
|
||||
compatible = "asahi-kasei,ak8963";
|
||||
reg = <0x0f>;
|
||||
// Currently only works in polling mode.
|
||||
// gpios = <&msmgpio 61 0>;
|
||||
vid-supply = <&pm8941_lvs1>;
|
||||
vdd-supply = <&pm8941_l17>;
|
||||
};
|
||||
|
||||
bmp280@76 {
|
||||
compatible = "bosch,bmp280";
|
||||
reg = <0x76>;
|
||||
vdda-supply = <&pm8941_lvs1>;
|
||||
vddd-supply = <&pm8941_l17>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@f9925000 {
|
||||
status = "ok";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
clock-frequency = <100000>;
|
||||
qcom,src-freq = <50000000>;
|
||||
|
||||
avago_apds993@39 {
|
||||
compatible = "avago,apds9930";
|
||||
reg = <0x39>;
|
||||
interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
|
||||
vdd-supply = <&pm8941_l17>;
|
||||
vddio-supply = <&pm8941_lvs1>;
|
||||
led-max-microamp = <100000>;
|
||||
amstaos,proximity-diodes = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 0xf04>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
compatible = "qcom,krait";
|
||||
|
|
@ -214,7 +214,7 @@
|
|||
|
||||
cpu-pmu {
|
||||
compatible = "qcom,krait-pmu";
|
||||
interrupts = <1 7 0xf04>;
|
||||
interrupts = <GIC_PPI 7 0xf04>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -233,17 +233,17 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 2 0xf08>,
|
||||
<1 3 0xf08>,
|
||||
<1 4 0xf08>,
|
||||
<1 1 0xf08>;
|
||||
interrupts = <GIC_PPI 2 0xf08>,
|
||||
<GIC_PPI 3 0xf08>,
|
||||
<GIC_PPI 4 0xf08>,
|
||||
<GIC_PPI 1 0xf08>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
adsp-pil {
|
||||
compatible = "qcom,msm8974-adsp-pil";
|
||||
|
||||
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
|
||||
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
|
|
@ -275,7 +275,7 @@
|
|||
qcom,smem = <443>, <429>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 8 10>;
|
||||
|
||||
|
|
@ -300,7 +300,7 @@
|
|||
qcom,smem = <435>, <428>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 8 14>;
|
||||
|
||||
|
|
@ -325,7 +325,7 @@
|
|||
qcom,smem = <451>, <431>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 8 18>;
|
||||
|
||||
|
|
@ -364,7 +364,7 @@
|
|||
|
||||
modem_smsm: modem@1 {
|
||||
reg = <1>;
|
||||
interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -372,7 +372,7 @@
|
|||
|
||||
adsp_smsm: adsp@2 {
|
||||
reg = <2>;
|
||||
interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
|
||||
wcnss_smsm: wcnss@7 {
|
||||
reg = <7>;
|
||||
interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -445,50 +445,50 @@
|
|||
|
||||
frame@f9021000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <0 8 0x4>,
|
||||
<0 7 0x4>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9021000 0x1000>,
|
||||
<0xf9022000 0x1000>;
|
||||
};
|
||||
|
||||
frame@f9023000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 9 0x4>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9023000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9024000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <0 10 0x4>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9024000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9025000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <0 11 0x4>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9025000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9026000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <0 12 0x4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9026000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9027000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <0 13 0x4>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9027000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <0 14 0x4>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -586,7 +586,7 @@
|
|||
blsp1_uart1: serial@f991d000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf991d000 0x1000>;
|
||||
interrupts = <0 107 0x0>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
|
@ -595,7 +595,7 @@
|
|||
blsp1_uart2: serial@f991e000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf991e000 0x1000>;
|
||||
interrupts = <0 108 0x0>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
|
@ -605,7 +605,8 @@
|
|||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
|
||||
reg-names = "hc_mem", "core_mem";
|
||||
interrupts = <0 123 0>, <0 138 0>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&gcc GCC_SDCC1_AHB_CLK>,
|
||||
|
|
@ -618,8 +619,8 @@
|
|||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
|
||||
reg-names = "hc_mem", "core_mem";
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 224 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
clocks = <&gcc GCC_SDCC3_APPS_CLK>,
|
||||
<&gcc GCC_SDCC3_AHB_CLK>,
|
||||
|
|
@ -632,7 +633,8 @@
|
|||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
||||
reg-names = "hc_mem", "core_mem";
|
||||
interrupts = <0 125 0>, <0 221 0>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&gcc GCC_SDCC2_AHB_CLK>,
|
||||
|
|
@ -699,25 +701,36 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 208 0>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c@f9924000 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,i2c-qup-v2.1.1";
|
||||
reg = <0xf9924000 0x1000>;
|
||||
interrupts = <0 96 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp_i2c3: i2c@f9925000 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,i2c-qup-v2.1.1";
|
||||
reg = <0xf9925000 0x1000>;
|
||||
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp_i2c8: i2c@f9964000 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,i2c-qup-v2.1.1";
|
||||
reg = <0xf9964000 0x1000>;
|
||||
interrupts = <0 102 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -728,7 +741,7 @@
|
|||
status = "disabled";
|
||||
compatible = "qcom,i2c-qup-v2.1.1";
|
||||
reg = <0xf9967000 0x1000>;
|
||||
interrupts = <0 105 IRQ_TYPE_NONE>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -737,6 +750,17 @@
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
blsp_i2c12: i2c@f9968000 {
|
||||
status = "disabled";
|
||||
compatible = "qcom,i2c-qup-v2.1.1";
|
||||
reg = <0xf9968000 0x1000>;
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spmi_bus: spmi@fc4cf000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg-names = "core", "intr", "cnfg";
|
||||
|
|
@ -744,7 +768,7 @@
|
|||
<0xfc4cb000 0x1000>,
|
||||
<0xfc4ca000 0x1000>;
|
||||
interrupt-names = "periph_irq";
|
||||
interrupts = <0 190 0>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,ee = <0>;
|
||||
qcom,channel = <0>;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -770,10 +794,11 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
port {
|
||||
etr_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out0>;
|
||||
in-ports {
|
||||
port {
|
||||
etr_in: endpoint {
|
||||
remote-endpoint = <&replicator_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -785,10 +810,11 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
port {
|
||||
tpiu_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&replicator_out1>;
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in: endpoint {
|
||||
remote-endpoint = <&replicator_out1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -800,7 +826,7 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
ports {
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -816,10 +842,11 @@
|
|||
remote-endpoint = <&tpiu_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf_out>;
|
||||
};
|
||||
};
|
||||
|
|
@ -833,20 +860,17 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
out-ports {
|
||||
port {
|
||||
etf_out: endpoint {
|
||||
remote-endpoint = <&replicator_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etf_in: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&merger_out>;
|
||||
};
|
||||
};
|
||||
|
|
@ -860,7 +884,7 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
ports {
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -873,12 +897,13 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
merger_in1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&funnel1_out>;
|
||||
};
|
||||
};
|
||||
port@8 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
merger_out: endpoint {
|
||||
remote-endpoint = <&etf_in>;
|
||||
};
|
||||
|
|
@ -893,7 +918,7 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
ports {
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -910,12 +935,13 @@
|
|||
port@5 {
|
||||
reg = <5>;
|
||||
funnel1_in5: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&kpss_out>;
|
||||
};
|
||||
};
|
||||
port@8 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel1_out: endpoint {
|
||||
remote-endpoint = <&merger_in1>;
|
||||
};
|
||||
|
|
@ -930,40 +956,38 @@
|
|||
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
||||
clock-names = "apb_pclk", "atclk";
|
||||
|
||||
ports {
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
kpss_in0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
kpss_in1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm1_out>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
kpss_in2: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm2_out>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
kpss_in3: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etm3_out>;
|
||||
};
|
||||
};
|
||||
port@8 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
kpss_out: endpoint {
|
||||
remote-endpoint = <&funnel1_in5>;
|
||||
};
|
||||
|
|
@ -980,9 +1004,11 @@
|
|||
|
||||
cpu = <&CPU0>;
|
||||
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint = <&kpss_in0>;
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint = <&kpss_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -996,9 +1022,11 @@
|
|||
|
||||
cpu = <&CPU1>;
|
||||
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint = <&kpss_in1>;
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint = <&kpss_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1012,9 +1040,11 @@
|
|||
|
||||
cpu = <&CPU2>;
|
||||
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint = <&kpss_in2>;
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint = <&kpss_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1028,9 +1058,11 @@
|
|||
|
||||
cpu = <&CPU3>;
|
||||
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint = <&kpss_in3>;
|
||||
out-ports {
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint = <&kpss_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1040,21 +1072,21 @@
|
|||
compatible = "qcom,smd";
|
||||
|
||||
adsp {
|
||||
interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 8 8>;
|
||||
qcom,smd-edge = <1>;
|
||||
};
|
||||
|
||||
modem {
|
||||
interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 8 12>;
|
||||
qcom,smd-edge = <0>;
|
||||
};
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue