Merge tag 'v5.4.47' into imx_5.4.y
* tag 'v5.4.47': (2193 commits) Linux 5.4.47 KVM: arm64: Save the host's PtrAuth keys in non-preemptible context KVM: arm64: Synchronize sysreg state on injecting an AArch32 exception ... Conflicts: arch/arm/boot/dts/imx6qdl.dtsi arch/arm/mach-imx/Kconfig arch/arm/mach-imx/common.h arch/arm/mach-imx/suspend-imx6.S arch/arm64/boot/dts/freescale/imx8qxp-mek.dts arch/powerpc/include/asm/cacheflush.h drivers/cpufreq/imx6q-cpufreq.c drivers/dma/imx-sdma.c drivers/edac/synopsys_edac.c drivers/firmware/imx/imx-scu.c drivers/net/ethernet/freescale/fec.h drivers/net/ethernet/freescale/fec_main.c drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c drivers/net/phy/phy_device.c drivers/perf/fsl_imx8_ddr_perf.c drivers/usb/cdns3/gadget.c drivers/usb/dwc3/gadget.c include/uapi/linux/dma-buf.h Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>5.4-rM2-2.2.x-imx-squashed
commit
5691e22711
|
@ -486,6 +486,7 @@ What: /sys/devices/system/cpu/vulnerabilities
|
|||
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
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/sys/devices/system/cpu/vulnerabilities/l1tf
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/sys/devices/system/cpu/vulnerabilities/mds
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||||
/sys/devices/system/cpu/vulnerabilities/srbds
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||||
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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Date: January 2018
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|
|
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@ -14,3 +14,4 @@ are configurable at compile, boot or run time.
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mds
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tsx_async_abort
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multihit.rst
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special-register-buffer-data-sampling.rst
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|
|
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@ -0,0 +1,149 @@
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.. SPDX-License-Identifier: GPL-2.0
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SRBDS - Special Register Buffer Data Sampling
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=============================================
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SRBDS is a hardware vulnerability that allows MDS :doc:`mds` techniques to
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infer values returned from special register accesses. Special register
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accesses are accesses to off core registers. According to Intel's evaluation,
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the special register reads that have a security expectation of privacy are
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RDRAND, RDSEED and SGX EGETKEY.
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When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
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to the core through the special register mechanism that is susceptible
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to MDS attacks.
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Affected processors
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--------------------
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Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED may
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be affected.
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A processor is affected by SRBDS if its Family_Model and stepping is
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in the following list, with the exception of the listed processors
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exporting MDS_NO while Intel TSX is available yet not enabled. The
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latter class of processors are only affected when Intel TSX is enabled
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by software using TSX_CTRL_MSR otherwise they are not affected.
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============= ============ ========
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common name Family_Model Stepping
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============= ============ ========
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IvyBridge 06_3AH All
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Haswell 06_3CH All
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Haswell_L 06_45H All
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Haswell_G 06_46H All
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Broadwell_G 06_47H All
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Broadwell 06_3DH All
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Skylake_L 06_4EH All
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Skylake 06_5EH All
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Kabylake_L 06_8EH <= 0xC
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Kabylake 06_9EH <= 0xD
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============= ============ ========
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Related CVEs
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------------
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The following CVE entry is related to this SRBDS issue:
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============== ===== =====================================
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CVE-2020-0543 SRBDS Special Register Buffer Data Sampling
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============== ===== =====================================
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Attack scenarios
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----------------
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An unprivileged user can extract values returned from RDRAND and RDSEED
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executed on another core or sibling thread using MDS techniques.
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Mitigation mechanism
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-------------------
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Intel will release microcode updates that modify the RDRAND, RDSEED, and
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EGETKEY instructions to overwrite secret special register data in the shared
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staging buffer before the secret data can be accessed by another logical
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processor.
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During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
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accesses from other logical processors will be delayed until the special
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register read is complete and the secret data in the shared staging buffer is
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overwritten.
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This has three effects on performance:
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#. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
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#. Executing RDRAND at the same time on multiple logical processors will be
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serialized, resulting in an overall reduction in the maximum RDRAND
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bandwidth.
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#. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
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logical processors that miss their core caches, with an impact similar to
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legacy locked cache-line-split accesses.
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The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
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the mitigation for RDRAND and RDSEED instructions executed outside of Intel
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Software Guard Extensions (Intel SGX) enclaves. On logical processors that
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disable the mitigation using this opt-out mechanism, RDRAND and RDSEED do not
|
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take longer to execute and do not impact performance of sibling logical
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processors memory accesses. The opt-out mechanism does not affect Intel SGX
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enclaves (including execution of RDRAND or RDSEED inside an enclave, as well
|
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as EGETKEY execution).
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IA32_MCU_OPT_CTRL MSR Definition
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--------------------------------
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Along with the mitigation for this issue, Intel added a new thread-scope
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IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
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RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL =
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9]==1. This MSR is introduced through the microcode update.
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Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
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disables the mitigation for RDRAND and RDSEED executed outside of an Intel SGX
|
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enclave on that logical processor. Opting out of the mitigation for a
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particular logical processor does not affect the RDRAND and RDSEED mitigations
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for other logical processors.
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Note that inside of an Intel SGX enclave, the mitigation is applied regardless
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of the value of RNGDS_MITG_DS.
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Mitigation control on the kernel command line
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---------------------------------------------
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The kernel command line allows control over the SRBDS mitigation at boot time
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with the option "srbds=". The option for this is:
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============= =============================================================
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off This option disables SRBDS mitigation for RDRAND and RDSEED on
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affected platforms.
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============= =============================================================
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SRBDS System Information
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-----------------------
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The Linux kernel provides vulnerability status information through sysfs. For
|
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SRBDS this can be accessed by the following sysfs file:
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/sys/devices/system/cpu/vulnerabilities/srbds
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|
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The possible values contained in this file are:
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|
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============================== =============================================
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Not affected Processor not vulnerable
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Vulnerable Processor vulnerable and mitigation disabled
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Vulnerable: No microcode Processor vulnerable and microcode is missing
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mitigation
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Mitigation: Microcode Processor is vulnerable and mitigation is in
|
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effect.
|
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Mitigation: TSX disabled Processor is only vulnerable when TSX is
|
||||
enabled while this system was booted with TSX
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disabled.
|
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Unknown: Dependent on
|
||||
hypervisor status Running on virtual guest processor that is
|
||||
affected but with no way to know if host
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||||
processor is mitigated or vulnerable.
|
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============================== =============================================
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SRBDS Default mitigation
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------------------------
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This new microcode serializes processor access during execution of RDRAND,
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RDSEED ensures that the shared buffer is overwritten before it is released for
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reuse. Use the "srbds=off" kernel command line to disable the mitigation for
|
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RDRAND and RDSEED.
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|
@ -136,6 +136,10 @@
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dynamic table installation which will install SSDT
|
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tables to /sys/firmware/acpi/tables/dynamic.
|
||||
|
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acpi_no_watchdog [HW,ACPI,WDT]
|
||||
Ignore the ACPI-based watchdog interface (WDAT) and let
|
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a native driver control the watchdog device instead.
|
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|
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acpi_rsdp= [ACPI,EFI,KEXEC]
|
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Pass the RSDP address to the kernel, mostly used
|
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on machines running EFI runtime service to boot the
|
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|
@ -2737,7 +2741,7 @@
|
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<name>,<region-number>[,<base>,<size>,<buswidth>,<altbuswidth>]
|
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|
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mtdparts= [MTD]
|
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See drivers/mtd/cmdlinepart.c.
|
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See drivers/mtd/parsers/cmdlinepart.c
|
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|
||||
multitce=off [PPC] This parameter disables the use of the pSeries
|
||||
firmware feature for updating multiple TCE entries
|
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|
@ -4575,6 +4579,26 @@
|
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spia_pedr=
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spia_peddr=
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|
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srbds= [X86,INTEL]
|
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Control the Special Register Buffer Data Sampling
|
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(SRBDS) mitigation.
|
||||
|
||||
Certain CPUs are vulnerable to an MDS-like
|
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exploit which can leak bits from the random
|
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number generator.
|
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|
||||
By default, this issue is mitigated by
|
||||
microcode. However, the microcode fix can cause
|
||||
the RDRAND and RDSEED instructions to become
|
||||
much slower. Among other effects, this will
|
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result in reduced throughput from /dev/urandom.
|
||||
|
||||
The microcode mitigation can be disabled with
|
||||
the following option:
|
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|
||||
off: Disable mitigation and remove
|
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performance impact to RDRAND and RDSEED
|
||||
|
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srcutree.counter_wrap_check [KNL]
|
||||
Specifies how frequently to check for
|
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grace-period sequence counter wrap for the
|
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|
@ -5001,8 +5025,7 @@
|
|||
|
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usbcore.old_scheme_first=
|
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[USB] Start with the old device initialization
|
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scheme, applies only to low and full-speed devices
|
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(default 0 = off).
|
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scheme (default 0 = off).
|
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|
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usbcore.usbfs_memory_mb=
|
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[USB] Memory limit (in MB) for buffers allocated by
|
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|
|
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@ -88,6 +88,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Neoverse-N1 | #1349291 | N/A |
|
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+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | MMU-500 | #841119,826419 | N/A |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
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+----------------+-----------------+-----------------+-----------------------------+
|
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|
|
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@ -110,6 +110,13 @@ PROPERTIES
|
|||
Usage: required
|
||||
Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
|
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|
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- fsl,erratum-a050385
|
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Usage: optional
|
||||
Value type: boolean
|
||||
Definition: A boolean property. Indicates the presence of the
|
||||
erratum A050385 which indicates that DMA transactions that are
|
||||
split can result in a FMan lock.
|
||||
|
||||
=============================================================================
|
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FMan MURAM Node
|
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|
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|
|
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@ -118,7 +118,7 @@ Tegra194:
|
|||
--------
|
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|
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pcie@14180000 {
|
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compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
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compatible = "nvidia,tegra194-pcie";
|
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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|
|
|
@ -850,3 +850,11 @@ business doing so.
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d_alloc_pseudo() is internal-only; uses outside of alloc_file_pseudo() are
|
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very suspect (and won't work in modules). Such uses are very likely to
|
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be misspelled d_alloc_anon().
|
||||
|
||||
---
|
||||
|
||||
**mandatory**
|
||||
|
||||
[should've been added in 2016] stale comment in finish_open() nonwithstanding,
|
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failure exits in ->atomic_open() instances should *NOT* fput() the file,
|
||||
no matter what. Everything is handled by the caller.
|
||||
|
|
|
@ -470,9 +470,9 @@ build.
|
|||
|
||||
The syntax of the Module.symvers file is::
|
||||
|
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<CRC> <Symbol> <Namespace> <Module> <Export Type>
|
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<CRC> <Symbol> <Module> <Export Type> <Namespace>
|
||||
|
||||
0xe1cc2a05 usb_stor_suspend USB_STORAGE drivers/usb/storage/usb-storage EXPORT_SYMBOL_GPL
|
||||
0xe1cc2a05 usb_stor_suspend drivers/usb/storage/usb-storage EXPORT_SYMBOL_GPL USB_STORAGE
|
||||
|
||||
The fields are separated by tabs and values may be empty (e.g.
|
||||
if no namespace is defined for an exported symbol).
|
||||
|
|
|
@ -159,11 +159,15 @@ Byte sequences
|
|||
distance = 16384 + (H << 14) + D
|
||||
state = S (copy S literals after this block)
|
||||
End of stream is reached if distance == 16384
|
||||
In version 1 only, to prevent ambiguity with the RLE case when
|
||||
((distance & 0x803f) == 0x803f) && (261 <= length <= 264), the
|
||||
compressor must not emit block copies where distance and length
|
||||
meet these conditions.
|
||||
|
||||
In version 1 only, this instruction is also used to encode a run of
|
||||
zeros if distance = 0xbfff, i.e. H = 1 and the D bits are all 1.
|
||||
zeros if distance = 0xbfff, i.e. H = 1 and the D bits are all 1.
|
||||
In this case, it is followed by a fourth byte, X.
|
||||
run length = ((X << 3) | (0 0 0 0 0 L L L)) + 4.
|
||||
run length = ((X << 3) | (0 0 0 0 0 L L L)) + 4
|
||||
|
||||
0 0 1 L L L L L (32..63)
|
||||
Copy of small block within 16kB distance (preferably less than 34B)
|
||||
|
|
|
@ -8,3 +8,4 @@ HD-Audio
|
|||
models
|
||||
controls
|
||||
dp-mst
|
||||
realtek-pc-beep
|
||||
|
|
|
@ -216,8 +216,6 @@ alc298-dell-aio
|
|||
ALC298 fixups on Dell AIO machines
|
||||
alc275-dell-xps
|
||||
ALC275 fixups on Dell XPS models
|
||||
alc256-dell-xps13
|
||||
ALC256 fixups on Dell XPS13
|
||||
lenovo-spk-noise
|
||||
Workaround for speaker noise on Lenovo machines
|
||||
lenovo-hotkey
|
||||
|
|
|
@ -0,0 +1,129 @@
|
|||
===============================
|
||||
Realtek PC Beep Hidden Register
|
||||
===============================
|
||||
|
||||
This file documents the "PC Beep Hidden Register", which is present in certain
|
||||
Realtek HDA codecs and controls a muxer and pair of passthrough mixers that can
|
||||
route audio between pins but aren't themselves exposed as HDA widgets. As far
|
||||
as I can tell, these hidden routes are designed to allow flexible PC Beep output
|
||||
for codecs that don't have mixer widgets in their output paths. Why it's easier
|
||||
to hide a mixer behind an undocumented vendor register than to just expose it
|
||||
as a widget, I have no idea.
|
||||
|
||||
Register Description
|
||||
====================
|
||||
|
||||
The register is accessed via processing coefficient 0x36 on NID 20h. Bits not
|
||||
identified below have no discernible effect on my machine, a Dell XPS 13 9350::
|
||||
|
||||
MSB LSB
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| |h|S|L| | B |R| | Known bits
|
||||
+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
|
||||
|0|0|1|1| 0x7 |0|0x0|1| 0x7 | Reset value
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
|
||||
1Ah input select (B): 2 bits
|
||||
When zero, expose the PC Beep line (from the internal beep generator, when
|
||||
enabled with the Set Beep Generation verb on NID 01h, or else from the
|
||||
external PCBEEP pin) on the 1Ah pin node. When nonzero, expose the headphone
|
||||
jack (or possibly Line In on some machines) input instead. If PC Beep is
|
||||
selected, the 1Ah boost control has no effect.
|
||||
|
||||
Amplify 1Ah loopback, left (L): 1 bit
|
||||
Amplify the left channel of 1Ah before mixing it into outputs as specified
|
||||
by h and S bits. Does not affect the level of 1Ah exposed to other widgets.
|
||||
|
||||
Amplify 1Ah loopback, right (R): 1 bit
|
||||
Amplify the right channel of 1Ah before mixing it into outputs as specified
|
||||
by h and S bits. Does not affect the level of 1Ah exposed to other widgets.
|
||||
|
||||
Loopback 1Ah to 21h [active low] (h): 1 bit
|
||||
When zero, mix 1Ah (possibly with amplification, depending on L and R bits)
|
||||
into 21h (headphone jack on my machine). Mixed signal respects the mute
|
||||
setting on 21h.
|
||||
|
||||
Loopback 1Ah to 14h (S): 1 bit
|
||||
When one, mix 1Ah (possibly with amplification, depending on L and R bits)
|
||||
into 14h (internal speaker on my machine). Mixed signal **ignores** the mute
|
||||
setting on 14h and is present whenever 14h is configured as an output.
|
||||
|
||||
Path diagrams
|
||||
=============
|
||||
|
||||
1Ah input selection (DIV is the PC Beep divider set on NID 01h)::
|
||||
|
||||
<Beep generator> <PCBEEP pin> <Headphone jack>
|
||||
| | |
|
||||
+--DIV--+--!DIV--+ {1Ah boost control}
|
||||
| |
|
||||
+--(b == 0)--+--(b != 0)--+
|
||||
|
|
||||
>1Ah (Beep/Headphone Mic/Line In)<
|
||||
|
||||
Loopback of 1Ah to 21h/14h::
|
||||
|
||||
<1Ah (Beep/Headphone Mic/Line In)>
|
||||
|
|
||||
{amplify if L/R}
|
||||
|
|
||||
+-----!h-----+-----S-----+
|
||||
| |
|
||||
{21h mute control} |
|
||||
| |
|
||||
>21h (Headphone)< >14h (Internal Speaker)<
|
||||
|
||||
Background
|
||||
==========
|
||||
|
||||
All Realtek HDA codecs have a vendor-defined widget with node ID 20h which
|
||||
provides access to a bank of registers that control various codec functions.
|
||||
Registers are read and written via the standard HDA processing coefficient
|
||||
verbs (Set/Get Coefficient Index, Set/Get Processing Coefficient). The node is
|
||||
named "Realtek Vendor Registers" in public datasheets' verb listings and,
|
||||
apart from that, is entirely undocumented.
|
||||
|
||||
This particular register, exposed at coefficient 0x36 and named in commits from
|
||||
Realtek, is of note: unlike most registers, which seem to control detailed
|
||||
amplifier parameters not in scope of the HDA specification, it controls audio
|
||||
routing which could just as easily have been defined using standard HDA mixer
|
||||
and selector widgets.
|
||||
|
||||
Specifically, it selects between two sources for the input pin widget with Node
|
||||
ID (NID) 1Ah: the widget's signal can come either from an audio jack (on my
|
||||
laptop, a Dell XPS 13 9350, it's the headphone jack, but comments in Realtek
|
||||
commits indicate that it might be a Line In on some machines) or from the PC
|
||||
Beep line (which is itself multiplexed between the codec's internal beep
|
||||
generator and external PCBEEP pin, depending on if the beep generator is
|
||||
enabled via verbs on NID 01h). Additionally, it can mix (with optional
|
||||
amplification) that signal onto the 21h and/or 14h output pins.
|
||||
|
||||
The register's reset value is 0x3717, corresponding to PC Beep on 1Ah that is
|
||||
then amplified and mixed into both the headphones and the speakers. Not only
|
||||
does this violate the HDA specification, which says that "[a vendor defined
|
||||
beep input pin] connection may be maintained *only* while the Link reset
|
||||
(**RST#**) is asserted", it means that we cannot ignore the register if we care
|
||||
about the input that 1Ah would otherwise expose or if the PCBEEP trace is
|
||||
poorly shielded and picks up chassis noise (both of which are the case on my
|
||||
machine).
|
||||
|
||||
Unfortunately, there are lots of ways to get this register configuration wrong.
|
||||
Linux, it seems, has gone through most of them. For one, the register resets
|
||||
after S3 suspend: judging by existing code, this isn't the case for all vendor
|
||||
registers, and it's led to some fixes that improve behavior on cold boot but
|
||||
don't last after suspend. Other fixes have successfully switched the 1Ah input
|
||||
away from PC Beep but have failed to disable both loopback paths. On my
|
||||
machine, this means that the headphone input is amplified and looped back to
|
||||
the headphone output, which uses the exact same pins! As you might expect, this
|
||||
causes terrible headphone noise, the character of which is controlled by the
|
||||
1Ah boost control. (If you've seen instructions online to fix XPS 13 headphone
|
||||
noise by changing "Headphone Mic Boost" in ALSA, now you know why.)
|
||||
|
||||
The information here has been obtained through black-box reverse engineering of
|
||||
the ALC256 codec's behavior and is not guaranteed to be correct. It likely
|
||||
also applies for the ALC255, ALC257, ALC235, and ALC236, since those codecs
|
||||
seem to be close relatives of the ALC256. (They all share one initialization
|
||||
function.) Additionally, other codecs like the ALC225 and ALC285 also have this
|
||||
register, judging by existing fixups in ``patch_realtek.c``, but specific
|
||||
data (e.g. node IDs, bit positions, pin mappings) for those codecs may differ
|
||||
from what I've described here.
|
29
Makefile
29
Makefile
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 24
|
||||
SUBLEVEL = 47
|
||||
EXTRAVERSION =
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
|
@ -707,12 +707,9 @@ else ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
|
|||
KBUILD_CFLAGS += -Os
|
||||
endif
|
||||
|
||||
ifdef CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED
|
||||
KBUILD_CFLAGS += -Wno-maybe-uninitialized
|
||||
endif
|
||||
|
||||
# Tell gcc to never replace conditional load with a non-conditional one
|
||||
KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0)
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-allow-store-data-races)
|
||||
|
||||
include scripts/Makefile.kcov
|
||||
include scripts/Makefile.gcc-plugins
|
||||
|
@ -860,6 +857,17 @@ KBUILD_CFLAGS += -Wno-pointer-sign
|
|||
# disable stringop warnings in gcc 8+
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)
|
||||
|
||||
# We'll want to enable this eventually, but it's not going away for 5.7 at least
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, zero-length-bounds)
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, array-bounds)
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-overflow)
|
||||
|
||||
# Another good warning that we'll want to enable eventually
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, restrict)
|
||||
|
||||
# Enabled with W=2, disabled by default as noisy
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
|
||||
|
||||
# disable invalid "can't wrap" optimizations for signed / pointers
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow)
|
||||
|
||||
|
@ -1237,12 +1245,16 @@ ifneq ($(dtstree),)
|
|||
%.dtb: include/config/kernel.release scripts_dtc
|
||||
$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@
|
||||
|
||||
PHONY += dtbs dtbs_install dt_binding_check
|
||||
dtbs dtbs_check: include/config/kernel.release scripts_dtc
|
||||
PHONY += dtbs dtbs_install dtbs_check
|
||||
dtbs: include/config/kernel.release scripts_dtc
|
||||
$(Q)$(MAKE) $(build)=$(dtstree)
|
||||
|
||||
ifneq ($(filter dtbs_check, $(MAKECMDGOALS)),)
|
||||
dtbs: dt_binding_check
|
||||
endif
|
||||
|
||||
dtbs_check: export CHECK_DTBS=1
|
||||
dtbs_check: dt_binding_check
|
||||
dtbs_check: dtbs
|
||||
|
||||
dtbs_install:
|
||||
$(Q)$(MAKE) $(dtbinst)=$(dtstree)
|
||||
|
@ -1257,6 +1269,7 @@ PHONY += scripts_dtc
|
|||
scripts_dtc: scripts_basic
|
||||
$(Q)$(MAKE) $(build)=scripts/dtc
|
||||
|
||||
PHONY += dt_binding_check
|
||||
dt_binding_check: scripts_dtc
|
||||
$(Q)$(MAKE) $(build)=Documentation/devicetree/bindings
|
||||
|
||||
|
|
|
@ -29,6 +29,8 @@
|
|||
.endm
|
||||
|
||||
#define ASM_NL ` /* use '`' to mark new line in macro */
|
||||
#define __ALIGN .align 4
|
||||
#define __ALIGN_STR __stringify(__ALIGN)
|
||||
|
||||
/* annotation for data we want in DCCM - if enabled in .config */
|
||||
.macro ARCFP_DATA nm
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/clocksource.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of.h>
|
||||
|
@ -409,12 +410,12 @@ static void arc_chk_core_config(void)
|
|||
if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
|
||||
panic("Linux built with incorrect DCCM Base address\n");
|
||||
|
||||
if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
|
||||
if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
|
||||
panic("Linux built with incorrect DCCM Size\n");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_ICCM
|
||||
if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
|
||||
if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
|
||||
panic("Linux built with incorrect ICCM Size\n");
|
||||
#endif
|
||||
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
menuconfig ARC_PLAT_EZNPS
|
||||
bool "\"EZchip\" ARC dev platform"
|
||||
depends on ISA_ARCOMPACT
|
||||
select CPU_BIG_ENDIAN
|
||||
select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
|
||||
select EZNPS_GIC
|
||||
|
|
|
@ -307,13 +307,15 @@ endif
|
|||
ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
|
||||
prepare: stack_protector_prepare
|
||||
stack_protector_prepare: prepare0
|
||||
$(eval KBUILD_CFLAGS += \
|
||||
$(eval SSP_PLUGIN_CFLAGS := \
|
||||
-fplugin-arg-arm_ssp_per_task_plugin-tso=$(shell \
|
||||
awk '{if ($$2 == "THREAD_SZ_ORDER") print $$3;}'\
|
||||
include/generated/asm-offsets.h) \
|
||||
-fplugin-arg-arm_ssp_per_task_plugin-offset=$(shell \
|
||||
awk '{if ($$2 == "TI_STACK_CANARY") print $$3;}'\
|
||||
include/generated/asm-offsets.h))
|
||||
$(eval KBUILD_CFLAGS += $(SSP_PLUGIN_CFLAGS))
|
||||
$(eval GCC_PLUGINS_CFLAGS += $(SSP_PLUGIN_CFLAGS))
|
||||
endif
|
||||
|
||||
all: $(notdir $(KBUILD_IMAGE))
|
||||
|
|
|
@ -101,7 +101,6 @@ clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S \
|
|||
$(libfdt) $(libfdt_hdrs) hyp-stub.S
|
||||
|
||||
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
|
||||
KBUILD_CFLAGS += $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
|
||||
|
||||
ifeq ($(CONFIG_FUNCTION_TRACER),y)
|
||||
ORIG_CFLAGS := $(KBUILD_CFLAGS)
|
||||
|
@ -117,7 +116,8 @@ CFLAGS_fdt_ro.o := $(nossp_flags)
|
|||
CFLAGS_fdt_rw.o := $(nossp_flags)
|
||||
CFLAGS_fdt_wip.o := $(nossp_flags)
|
||||
|
||||
ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin -I$(obj)
|
||||
ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \
|
||||
-I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
|
||||
asflags-y := -DZIMAGE
|
||||
|
||||
# Supply kernel BSS size to the decompressor via a linker symbol.
|
||||
|
|
|
@ -43,7 +43,7 @@ SECTIONS
|
|||
}
|
||||
.table : ALIGN(4) {
|
||||
_table_start = .;
|
||||
LONG(ZIMAGE_MAGIC(2))
|
||||
LONG(ZIMAGE_MAGIC(4))
|
||||
LONG(ZIMAGE_MAGIC(0x5a534c4b))
|
||||
LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start))
|
||||
LONG(ZIMAGE_MAGIC(_kernel_bss_size))
|
||||
|
|
|
@ -526,11 +526,11 @@
|
|||
* Supply voltage supervisor on board will not allow opp50 so
|
||||
* disable it and set opp100 as suspend OPP.
|
||||
*/
|
||||
opp50@300000000 {
|
||||
opp50-300000000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
opp100@600000000 {
|
||||
opp100-600000000 {
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -125,8 +125,6 @@
|
|||
bus-width = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdmmc0_default>;
|
||||
non-removable;
|
||||
mmc-ddr-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -75,7 +75,7 @@
|
|||
timer@20200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x20200 0x100>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
|
@ -83,7 +83,7 @@
|
|||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x20600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
|
@ -91,7 +91,7 @@
|
|||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x20620 0x20>;
|
||||
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -112,6 +112,7 @@
|
|||
&sdhci {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
|
||||
bus-width = <4>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
|
|
|
@ -488,6 +488,7 @@
|
|||
"dsi0_ddr2",
|
||||
"dsi0_ddr";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal: thermal@7e212000 {
|
||||
|
|
|
@ -24,12 +24,12 @@
|
|||
|
||||
&cpsw_emac0 {
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy-handle = <ðphy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
|
|
|
@ -33,12 +33,12 @@
|
|||
|
||||
&cpsw_emac0 {
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy-handle = <ðphy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
|
|
|
@ -24,12 +24,12 @@
|
|||
|
||||
&cpsw_emac0 {
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy-handle = <ðphy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
|
|
|
@ -3413,6 +3413,7 @@
|
|||
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -3441,6 +3442,7 @@
|
|||
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -3469,6 +3471,7 @@
|
|||
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -3497,6 +3500,7 @@
|
|||
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -148,6 +148,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0xc0000000>;
|
||||
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2";
|
||||
reg = <0x0 0x44000000 0x0 0x1000000>,
|
||||
<0x0 0x45000000 0x0 0x1000>;
|
||||
|
@ -171,6 +172,7 @@
|
|||
#address-cells = <1>;
|
||||
ranges = <0x51000000 0x51000000 0x3000
|
||||
0x0 0x20000000 0x10000000>;
|
||||
dma-ranges;
|
||||
/**
|
||||
* To enable PCI endpoint mode, disable the pcie1_rc
|
||||
* node and enable pcie1_ep mode.
|
||||
|
@ -228,6 +230,7 @@
|
|||
#address-cells = <1>;
|
||||
ranges = <0x51800000 0x51800000 0x3000
|
||||
0x0 0x30000000 0x10000000>;
|
||||
dma-ranges;
|
||||
status = "disabled";
|
||||
pcie2_rc: pcie@51800000 {
|
||||
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
|
||||
|
|
|
@ -86,3 +86,8 @@
|
|||
&usb4_tm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
/* dra76x is not affected by i887 */
|
||||
max-frequency = <96000000>;
|
||||
};
|
||||
|
|
|
@ -796,16 +796,6 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x0520>;
|
||||
assigned-clocks = <&ipu1_gfclk_mux>;
|
||||
assigned-clock-parents = <&dpll_core_h22x2_ck>;
|
||||
};
|
||||
|
||||
dummy_ck: dummy_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
@ -1564,6 +1554,8 @@
|
|||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
|
||||
assigned-clock-parents = <&dpll_core_h22x2_ck>;
|
||||
};
|
||||
|
||||
ipu_clkctrl: ipu-clkctrl@50 {
|
||||
|
|
|
@ -115,7 +115,7 @@
|
|||
gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>;
|
||||
gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <1>;
|
||||
cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>;
|
||||
cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
lcd@0 {
|
||||
compatible = "samsung,ld9040";
|
||||
|
@ -124,8 +124,6 @@
|
|||
vci-supply = <&ldo17_reg>;
|
||||
reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
|
||||
spi-max-frequency = <1200000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
power-on-delay = <10>;
|
||||
reset-delay = <10>;
|
||||
panel-width-mm = <90>;
|
||||
|
|
|
@ -75,8 +75,8 @@
|
|||
imx27-phycard-s-rdk {
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
|
||||
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
|
||||
MX27_PAD_I2C_DATA__I2C_DATA 0x0
|
||||
MX27_PAD_I2C_CLK__I2C_CLK 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
@ -38,7 +38,7 @@
|
|||
};
|
||||
|
||||
&switch_ports {
|
||||
/delete-node/ port@2;
|
||||
/delete-node/ port@3;
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
|
|
|
@ -65,13 +65,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -65,13 +65,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -53,17 +53,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
fsl,dual-channel;
|
||||
status = "okay";
|
||||
|
|
|
@ -377,3 +377,18 @@
|
|||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
|
||||
};
|
||||
|
|
|
@ -107,14 +107,14 @@
|
|||
regulators {
|
||||
vdd_arm: buck1 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <730000>;
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1380000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_soc: buck2 {
|
||||
regulator-name = "vdd_soc";
|
||||
regulator-min-microvolt = <730000>;
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1380000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
@ -183,7 +183,6 @@
|
|||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
vmmc-supply = <&vdd_emmc_1p8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -153,6 +153,7 @@
|
|||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&pwrseq_ti_wifi>;
|
||||
cap-power-off-card;
|
||||
non-removable;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
/* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */
|
||||
|
|
|
@ -92,7 +92,6 @@
|
|||
};
|
||||
|
||||
&fec {
|
||||
/delete-property/interrupts-extended;
|
||||
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
|
@ -337,7 +337,6 @@
|
|||
assigned-clock-rates = <400000000>;
|
||||
bus-width = <8>;
|
||||
fsl,tuning-step = <2>;
|
||||
max-frequency = <100000000>;
|
||||
vmmc-supply = <®_module_3v3>;
|
||||
vqmmc-supply = <®_DCDC3>;
|
||||
non-removable;
|
||||
|
@ -347,7 +346,7 @@
|
|||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
|
||||
&pinctrl_gpio7>;
|
||||
&pinctrl_gpio7 &pinctrl_usbc_det>;
|
||||
|
||||
pinctrl_gpio1: gpio1-grp {
|
||||
fsl,pins = <
|
||||
|
@ -452,7 +451,6 @@
|
|||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
|
||||
|
@ -650,6 +648,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbc_det: gpio-usbc-det {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh_reg: gpio-usbh-vbus {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
|
||||
|
|
|
@ -734,7 +734,7 @@
|
|||
};
|
||||
|
||||
mdio0: mdio@2d24000 {
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
compatible = "gianfar";
|
||||
device_type = "mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -743,7 +743,7 @@
|
|||
};
|
||||
|
||||
mdio1: mdio@2d64000 {
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
compatible = "gianfar";
|
||||
device_type = "mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
@ -849,34 +849,46 @@
|
|||
compatible = "ti,omap2-onenand";
|
||||
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
|
||||
|
||||
/*
|
||||
* These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
|
||||
* bootloader set values when booted with v5.1
|
||||
* (OneNAND Manufacturer: Samsung):
|
||||
*
|
||||
* cs0 GPMC_CS_CONFIG1: 0xfb001202
|
||||
* cs0 GPMC_CS_CONFIG2: 0x00111100
|
||||
* cs0 GPMC_CS_CONFIG3: 0x00020200
|
||||
* cs0 GPMC_CS_CONFIG4: 0x11001102
|
||||
* cs0 GPMC_CS_CONFIG5: 0x03101616
|
||||
* cs0 GPMC_CS_CONFIG6: 0x90060000
|
||||
*/
|
||||
gpmc,sync-read;
|
||||
gpmc,sync-write;
|
||||
gpmc,burst-length = <16>;
|
||||
gpmc,burst-read;
|
||||
gpmc,burst-wrap;
|
||||
gpmc,burst-write;
|
||||
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
|
||||
gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,mux-add-data = <2>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <87>;
|
||||
gpmc,cs-wr-off-ns = <87>;
|
||||
gpmc,cs-rd-off-ns = <102>;
|
||||
gpmc,cs-wr-off-ns = <102>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <10>;
|
||||
gpmc,adv-wr-off-ns = <10>;
|
||||
gpmc,oe-on-ns = <15>;
|
||||
gpmc,oe-off-ns = <87>;
|
||||
gpmc,adv-rd-off-ns = <12>;
|
||||
gpmc,adv-wr-off-ns = <12>;
|
||||
gpmc,oe-on-ns = <12>;
|
||||
gpmc,oe-off-ns = <102>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <87>;
|
||||
gpmc,rd-cycle-ns = <112>;
|
||||
gpmc,wr-cycle-ns = <112>;
|
||||
gpmc,access-ns = <81>;
|
||||
gpmc,page-burst-access-ns = <15>;
|
||||
gpmc,we-off-ns = <102>;
|
||||
gpmc,rd-cycle-ns = <132>;
|
||||
gpmc,wr-cycle-ns = <132>;
|
||||
gpmc,access-ns = <96>;
|
||||
gpmc,page-burst-access-ns = <18>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,clk-activation-ns = <5>;
|
||||
gpmc,wr-data-mux-bus-ns = <30>;
|
||||
gpmc,wr-access-ns = <81>;
|
||||
gpmc,clk-activation-ns = <6>;
|
||||
gpmc,wr-data-mux-bus-ns = <36>;
|
||||
gpmc,wr-access-ns = <96>;
|
||||
gpmc,sync-clk-ps = <15000>;
|
||||
|
||||
/*
|
||||
|
|
|
@ -143,6 +143,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xc0000000>;
|
||||
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
reg = <0 0x44000000 0 0x2000>,
|
||||
<0 0x44800000 0 0x3000>,
|
||||
|
|
|
@ -323,8 +323,8 @@
|
|||
interrupt-controller;
|
||||
reg = <0 0x200>;
|
||||
#interrupt-cells = <1>;
|
||||
valid-mask = <0xFFFFFFFF>;
|
||||
clear-mask = <0>;
|
||||
valid-mask = <0xffffffff>;
|
||||
clear-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
timer0: timer@200 {
|
||||
|
|
|
@ -240,8 +240,8 @@
|
|||
reg = <0 0x200>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
valid-mask = <0xFFFFFFFF>;
|
||||
clear-mask = <0>;
|
||||
valid-mask = <0xffffffff>;
|
||||
clear-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
timer0: timer@200 {
|
||||
|
|
|
@ -131,7 +131,14 @@
|
|||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&pd_c5>;
|
||||
|
|
|
@ -479,7 +479,7 @@
|
|||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extalr_clk>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
|
|
|
@ -128,7 +128,7 @@
|
|||
assigned-clocks = <&cru SCLK_GPU>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
resets = <&cru SRST_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -58,20 +58,25 @@
|
|||
|
||||
lvds-encoder {
|
||||
compatible = "ti,sn75lvds83", "lvds-encoder";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds_in_vop0: endpoint {
|
||||
remote-endpoint = <&vop0_out_lvds>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
lvds_in_vop0: endpoint {
|
||||
remote-endpoint = <&vop0_out_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lvds_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -465,7 +470,7 @@
|
|||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
|
||||
vmmcq-supply = <&vccio_wl>;
|
||||
vqmmc-supply = <&vccio_wl>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: phy@0 {
|
||||
phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
clocks = <&cru SCLK_MAC_PHY>;
|
||||
|
|
|
@ -150,7 +150,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: phy@0 {
|
||||
phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id1234.d400",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
|
|
|
@ -561,7 +561,7 @@
|
|||
"pp1",
|
||||
"ppmmu1";
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
resets = <&cru SRST_GPU_A>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1033,7 +1033,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi-0 {
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
@ -1051,7 +1051,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi-1 {
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
|
|
@ -84,7 +84,7 @@
|
|||
compatible = "arm,mali-400";
|
||||
reg = <0x10090000 0x10000>;
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
assigned-clocks = <&cru ACLK_GPU>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_GPU>;
|
||||
|
|
|
@ -358,8 +358,8 @@
|
|||
};
|
||||
|
||||
®_dldo3 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vdd-csi";
|
||||
};
|
||||
|
||||
|
@ -482,7 +482,8 @@
|
|||
};
|
||||
|
||||
&usbphy {
|
||||
usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
|
||||
usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */
|
||||
usb0_vbus_power-supply = <&usb_power_supply>;
|
||||
usb0_vbus-supply = <®_drivevbus>;
|
||||
usb1_vbus-supply = <®_vmain>;
|
||||
usb2_vbus-supply = <®_vmain>;
|
||||
|
|
|
@ -313,7 +313,7 @@
|
|||
|
||||
display_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-a83t-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
reg = <0x01000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_PLL_DE>;
|
||||
clock-names = "bus",
|
||||
|
|
|
@ -118,7 +118,7 @@
|
|||
display_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-r40-de2-clk",
|
||||
"allwinner,sun8i-h3-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
reg = <0x01000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
|
@ -266,6 +266,16 @@
|
|||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
ahci: sata@1c18000 {
|
||||
compatible = "allwinner,sun8i-r40-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
|
||||
resets = <&ccu RST_BUS_SATA>;
|
||||
reset-names = "ahci";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@1c19000 {
|
||||
compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
|
||||
reg = <0x01c19000 0x100>;
|
||||
|
@ -557,17 +567,6 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ahci: sata@1c18000 {
|
||||
compatible = "allwinner,sun8i-r40-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
|
||||
resets = <&ccu RST_BUS_SATA>;
|
||||
reset-names = "ahci";
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
gmac: ethernet@1c50000 {
|
||||
compatible = "allwinner,sun8i-r40-gmac";
|
||||
syscon = <&ccu>;
|
||||
|
|
|
@ -105,7 +105,7 @@
|
|||
|
||||
display_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-v3s-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
reg = <0x01000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
|
|
|
@ -113,7 +113,7 @@
|
|||
|
||||
display_clocks: clock@1000000 {
|
||||
/* compatible is in per SoC .dtsi file */
|
||||
reg = <0x01000000 0x100000>;
|
||||
reg = <0x01000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
|
|
|
@ -30,7 +30,7 @@ static int nhpoly1305_neon_update(struct shash_desc *desc,
|
|||
return crypto_nhpoly1305_update(desc, src, srclen);
|
||||
|
||||
do {
|
||||
unsigned int n = min_t(unsigned int, srclen, PAGE_SIZE);
|
||||
unsigned int n = min_t(unsigned int, srclen, SZ_4K);
|
||||
|
||||
kernel_neon_begin();
|
||||
crypto_nhpoly1305_update_helper(desc, src, n, _nh_neon);
|
||||
|
|
|
@ -18,11 +18,11 @@
|
|||
#endif
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/domain.h>
|
||||
#include <asm/opcodes-virt.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/uaccess-asm.h>
|
||||
|
||||
#define IOMEM(x) (x)
|
||||
|
||||
|
@ -446,79 +446,6 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
|
|||
.size \name , . - \name
|
||||
.endm
|
||||
|
||||
.macro csdb
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
.inst.w 0xf3af8014
|
||||
#else
|
||||
.inst 0xe320f014
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
|
||||
#ifndef CONFIG_CPU_USE_DOMAINS
|
||||
adds \tmp, \addr, #\size - 1
|
||||
sbcscc \tmp, \tmp, \limit
|
||||
bcs \bad
|
||||
#ifdef CONFIG_CPU_SPECTRE
|
||||
movcs \addr, #0
|
||||
csdb
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
|
||||
#ifdef CONFIG_CPU_SPECTRE
|
||||
sub \tmp, \limit, #1
|
||||
subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
|
||||
addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
|
||||
subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
|
||||
movlo \addr, #0 @ if (tmp < 0) addr = NULL
|
||||
csdb
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_disable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_DISABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_enable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_ENABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_save, tmp
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
mrc p15, 0, \tmp, c3, c0, 0
|
||||
str \tmp, [sp, #SVC_DACR]
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_restore
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
ldr r0, [sp, #SVC_DACR]
|
||||
mcr p15, 0, r0, c3, c0, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
|
||||
.macro ret\c, reg
|
||||
#if __LINUX_ARM_ARCH__ < 6
|
||||
|
|
|
@ -164,8 +164,13 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
|
|||
preempt_enable();
|
||||
#endif
|
||||
|
||||
if (!ret)
|
||||
*oval = oldval;
|
||||
/*
|
||||
* Store unconditionally. If ret != 0 the extra store is the least
|
||||
* of the worries but GCC cannot figure out that __futex_atomic_op()
|
||||
* is either setting ret to -EFAULT or storing the old value in
|
||||
* oldval which results in a uninitialized warning at the call site.
|
||||
*/
|
||||
*oval = oldval;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -363,6 +363,7 @@ static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
|
|||
}
|
||||
}
|
||||
|
||||
static inline void vcpu_ptrauth_setup_lazy(struct kvm_vcpu *vcpu) {}
|
||||
static inline bool vcpu_has_ptrauth(struct kvm_vcpu *vcpu) { return false; }
|
||||
static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) { }
|
||||
|
||||
#endif /* __ARM_KVM_EMULATE_H__ */
|
||||
|
|
|
@ -421,4 +421,6 @@ static inline bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
|
|||
return true;
|
||||
}
|
||||
|
||||
#define kvm_arm_vcpu_loaded(vcpu) (false)
|
||||
|
||||
#endif /* __ARM_KVM_HOST_H__ */
|
||||
|
|
|
@ -0,0 +1,117 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __ASM_UACCESS_ASM_H__
|
||||
#define __ASM_UACCESS_ASM_H__
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/domain.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
.macro csdb
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
.inst.w 0xf3af8014
|
||||
#else
|
||||
.inst 0xe320f014
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
|
||||
#ifndef CONFIG_CPU_USE_DOMAINS
|
||||
adds \tmp, \addr, #\size - 1
|
||||
sbcscc \tmp, \tmp, \limit
|
||||
bcs \bad
|
||||
#ifdef CONFIG_CPU_SPECTRE
|
||||
movcs \addr, #0
|
||||
csdb
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
|
||||
#ifdef CONFIG_CPU_SPECTRE
|
||||
sub \tmp, \limit, #1
|
||||
subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
|
||||
addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
|
||||
subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
|
||||
movlo \addr, #0 @ if (tmp < 0) addr = NULL
|
||||
csdb
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_disable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_DISABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_enable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_ENABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#if defined(CONFIG_CPU_SW_DOMAIN_PAN) || defined(CONFIG_CPU_USE_DOMAINS)
|
||||
#define DACR(x...) x
|
||||
#else
|
||||
#define DACR(x...)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Save the address limit on entry to a privileged exception.
|
||||
*
|
||||
* If we are using the DACR for kernel access by the user accessors
|
||||
* (CONFIG_CPU_USE_DOMAINS=y), always reset the DACR kernel domain
|
||||
* back to client mode, whether or not \disable is set.
|
||||
*
|
||||
* If we are using SW PAN, set the DACR user domain to no access
|
||||
* if \disable is set.
|
||||
*/
|
||||
.macro uaccess_entry, tsk, tmp0, tmp1, tmp2, disable
|
||||
ldr \tmp1, [\tsk, #TI_ADDR_LIMIT]
|
||||
mov \tmp2, #TASK_SIZE
|
||||
str \tmp2, [\tsk, #TI_ADDR_LIMIT]
|
||||
DACR( mrc p15, 0, \tmp0, c3, c0, 0)
|
||||
DACR( str \tmp0, [sp, #SVC_DACR])
|
||||
str \tmp1, [sp, #SVC_ADDR_LIMIT]
|
||||
.if \disable && IS_ENABLED(CONFIG_CPU_SW_DOMAIN_PAN)
|
||||
/* kernel=client, user=no access */
|
||||
mov \tmp2, #DACR_UACCESS_DISABLE
|
||||
mcr p15, 0, \tmp2, c3, c0, 0
|
||||
instr_sync
|
||||
.elseif IS_ENABLED(CONFIG_CPU_USE_DOMAINS)
|
||||
/* kernel=client */
|
||||
bic \tmp2, \tmp0, #domain_mask(DOMAIN_KERNEL)
|
||||
orr \tmp2, \tmp2, #domain_val(DOMAIN_KERNEL, DOMAIN_CLIENT)
|
||||
mcr p15, 0, \tmp2, c3, c0, 0
|
||||
instr_sync
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/* Restore the user access state previously saved by uaccess_entry */
|
||||
.macro uaccess_exit, tsk, tmp0, tmp1
|
||||
ldr \tmp1, [sp, #SVC_ADDR_LIMIT]
|
||||
DACR( ldr \tmp0, [sp, #SVC_DACR])
|
||||
str \tmp1, [\tsk, #TI_ADDR_LIMIT]
|
||||
DACR( mcr p15, 0, \tmp0, c3, c0, 0)
|
||||
.endm
|
||||
|
||||
#undef DACR
|
||||
|
||||
#endif /* __ASM_UACCESS_ASM_H__ */
|
|
@ -27,6 +27,7 @@
|
|||
#include <asm/unistd.h>
|
||||
#include <asm/tls.h>
|
||||
#include <asm/system_info.h>
|
||||
#include <asm/uaccess-asm.h>
|
||||
|
||||
#include "entry-header.S"
|
||||
#include <asm/entry-macro-multi.S>
|
||||
|
@ -179,15 +180,7 @@ ENDPROC(__und_invalid)
|
|||
stmia r7, {r2 - r6}
|
||||
|
||||
get_thread_info tsk
|
||||
ldr r0, [tsk, #TI_ADDR_LIMIT]
|
||||
mov r1, #TASK_SIZE
|
||||
str r1, [tsk, #TI_ADDR_LIMIT]
|
||||
str r0, [sp, #SVC_ADDR_LIMIT]
|
||||
|
||||
uaccess_save r0
|
||||
.if \uaccess
|
||||
uaccess_disable r0
|
||||
.endif
|
||||
uaccess_entry tsk, r0, r1, r2, \uaccess
|
||||
|
||||
.if \trace
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/uaccess-asm.h>
|
||||
#include <asm/v7m.h>
|
||||
|
||||
@ Bad Abort numbers
|
||||
|
@ -217,9 +218,7 @@
|
|||
blne trace_hardirqs_off
|
||||
#endif
|
||||
.endif
|
||||
ldr r1, [sp, #SVC_ADDR_LIMIT]
|
||||
uaccess_restore
|
||||
str r1, [tsk, #TI_ADDR_LIMIT]
|
||||
uaccess_exit tsk, r0, r1
|
||||
|
||||
#ifndef CONFIG_THUMB2_KERNEL
|
||||
@ ARM mode SVC restore
|
||||
|
@ -263,9 +262,7 @@
|
|||
@ on the stack remains correct).
|
||||
@
|
||||
.macro svc_exit_via_fiq
|
||||
ldr r1, [sp, #SVC_ADDR_LIMIT]
|
||||
uaccess_restore
|
||||
str r1, [tsk, #TI_ADDR_LIMIT]
|
||||
uaccess_exit tsk, r0, r1
|
||||
#ifndef CONFIG_THUMB2_KERNEL
|
||||
@ ARM mode restore
|
||||
mov r0, sp
|
||||
|
|
|
@ -219,8 +219,8 @@ static struct undef_hook arm_break_hook = {
|
|||
};
|
||||
|
||||
static struct undef_hook thumb_break_hook = {
|
||||
.instr_mask = 0xffff,
|
||||
.instr_val = 0xde01,
|
||||
.instr_mask = 0xffffffff,
|
||||
.instr_val = 0x0000de01,
|
||||
.cpsr_mask = PSR_T_BIT,
|
||||
.cpsr_val = PSR_T_BIT,
|
||||
.fn = break_trap,
|
||||
|
|
|
@ -92,6 +92,8 @@ static bool __init cntvct_functional(void)
|
|||
* this.
|
||||
*/
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
|
||||
if (!np)
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,armv8-timer");
|
||||
if (!np)
|
||||
goto out_put;
|
||||
|
||||
|
|
|
@ -118,7 +118,7 @@ ENTRY(arm_copy_from_user)
|
|||
|
||||
ENDPROC(arm_copy_from_user)
|
||||
|
||||
.pushsection .fixup,"ax"
|
||||
.pushsection .text.fixup,"ax"
|
||||
.align 0
|
||||
copy_abort_preamble
|
||||
ldmfd sp!, {r1, r2, r3}
|
||||
|
|
|
@ -587,7 +587,7 @@ config SOC_IMX7D
|
|||
select PINCTRL_IMX7D
|
||||
select SOC_IMX7D_CA7 if ARCH_MULTI_V7
|
||||
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
|
||||
select ARM_ERRATA_814220
|
||||
select ARM_ERRATA_814220 if ARCH_MULTI_V7
|
||||
help
|
||||
This enables support for Freescale i.MX7 Dual processor.
|
||||
|
||||
|
|
|
@ -118,6 +118,10 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
|
|||
obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
|
||||
obj-$(CONFIG_SOC_IMX7ULP) += suspend-imx7ulp.o
|
||||
endif
|
||||
ifeq ($(CONFIG_ARM_CPU_SUSPEND),y)
|
||||
AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
|
||||
endif
|
||||
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX1) += mach-imx1.o
|
||||
|
|
|
@ -168,7 +168,6 @@ void imx_cpu_die(unsigned int cpu);
|
|||
int imx_cpu_kill(unsigned int cpu);
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
void v7_cpu_resume(void);
|
||||
void ca7_cpu_resume(void);
|
||||
void imx53_suspend(void __iomem *ocram_vbase);
|
||||
extern const u32 imx53_suspend_sz;
|
||||
|
@ -177,7 +176,6 @@ void imx7_suspend(void __iomem *ocram_vbase);
|
|||
void imx7ulp_cpu_resume(void);
|
||||
void imx7ulp_suspend(void __iomem *ocram_vbase);
|
||||
#else
|
||||
static inline void v7_cpu_resume(void) {}
|
||||
static inline void ca7_cpu_resume(void) {}
|
||||
static inline void imx53_suspend(void __iomem *ocram_vbase) {}
|
||||
static const u32 imx53_suspend_sz;
|
||||
|
@ -193,6 +191,8 @@ int imx_ddrc_get_ddr_type(void);
|
|||
static inline int imx_ddrc_get_ddr_type(void) { return 0; }
|
||||
#endif
|
||||
|
||||
void v7_cpu_resume(void);
|
||||
|
||||
void imx6_pm_ccm_init(const char *ccm_compat);
|
||||
void imx6q_pm_init(void);
|
||||
void imx6dl_pm_init(void);
|
||||
|
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "hardware.h"
|
||||
|
||||
/*
|
||||
* The following code must assume it is running from physical address
|
||||
* where absolute virtual addresses to the data section have to be
|
||||
* turned into relative ones.
|
||||
*/
|
||||
|
||||
ENTRY(v7_cpu_resume)
|
||||
bl v7_invalidate_l1
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
bl l2c310_early_resume
|
||||
#endif
|
||||
b cpu_resume
|
||||
ENDPROC(v7_cpu_resume)
|
|
@ -729,20 +729,3 @@ dsm_resume_mmdc_done:
|
|||
|
||||
ret lr
|
||||
ENDPROC(imx6_suspend)
|
||||
|
||||
/*
|
||||
* The following code must assume it is running from physical address
|
||||
* where absolute virtual addresses to the data section have to be
|
||||
* turned into relative ones.
|
||||
*/
|
||||
|
||||
ENTRY(v7_cpu_resume)
|
||||
bl v7_invalidate_l1
|
||||
is_cortex_a7
|
||||
beq done
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
bl l2c310_early_resume
|
||||
#endif
|
||||
done:
|
||||
b cpu_resume
|
||||
ENDPROC(v7_cpu_resume)
|
||||
|
|
|
@ -929,7 +929,11 @@ static inline void emit_a32_rsh_i64(const s8 dst[],
|
|||
rd = arm_bpf_get_reg64(dst, tmp, ctx);
|
||||
|
||||
/* Do LSR operation */
|
||||
if (val < 32) {
|
||||
if (val == 0) {
|
||||
/* An immediate value of 0 encodes a shift amount of 32
|
||||
* for LSR. To shift by 0, don't do anything.
|
||||
*/
|
||||
} else if (val < 32) {
|
||||
emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
|
||||
emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
|
||||
emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx);
|
||||
|
@ -955,7 +959,11 @@ static inline void emit_a32_arsh_i64(const s8 dst[],
|
|||
rd = arm_bpf_get_reg64(dst, tmp, ctx);
|
||||
|
||||
/* Do ARSH operation */
|
||||
if (val < 32) {
|
||||
if (val == 0) {
|
||||
/* An immediate value of 0 encodes a shift amount of 32
|
||||
* for ASR. To shift by 0, don't do anything.
|
||||
*/
|
||||
} else if (val < 32) {
|
||||
emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
|
||||
emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
|
||||
emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx);
|
||||
|
@ -992,21 +1000,35 @@ static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[],
|
|||
arm_bpf_put_reg32(dst_hi, rd[0], ctx);
|
||||
}
|
||||
|
||||
static bool is_ldst_imm(s16 off, const u8 size)
|
||||
{
|
||||
s16 off_max = 0;
|
||||
|
||||
switch (size) {
|
||||
case BPF_B:
|
||||
case BPF_W:
|
||||
off_max = 0xfff;
|
||||
break;
|
||||
case BPF_H:
|
||||
off_max = 0xff;
|
||||
break;
|
||||
case BPF_DW:
|
||||
/* Need to make sure off+4 does not overflow. */
|
||||
off_max = 0xfff - 4;
|
||||
break;
|
||||
}
|
||||
return -off_max <= off && off <= off_max;
|
||||
}
|
||||
|
||||
/* *(size *)(dst + off) = src */
|
||||
static inline void emit_str_r(const s8 dst, const s8 src[],
|
||||
s32 off, struct jit_ctx *ctx, const u8 sz){
|
||||
s16 off, struct jit_ctx *ctx, const u8 sz){
|
||||
const s8 *tmp = bpf2a32[TMP_REG_1];
|
||||
s32 off_max;
|
||||
s8 rd;
|
||||
|
||||
rd = arm_bpf_get_reg32(dst, tmp[1], ctx);
|
||||
|
||||
if (sz == BPF_H)
|
||||
off_max = 0xff;
|
||||
else
|
||||
off_max = 0xfff;
|
||||
|
||||
if (off < 0 || off > off_max) {
|
||||
if (!is_ldst_imm(off, sz)) {
|
||||
emit_a32_mov_i(tmp[0], off, ctx);
|
||||
emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx);
|
||||
rd = tmp[0];
|
||||
|
@ -1035,18 +1057,12 @@ static inline void emit_str_r(const s8 dst, const s8 src[],
|
|||
|
||||
/* dst = *(size*)(src + off) */
|
||||
static inline void emit_ldx_r(const s8 dst[], const s8 src,
|
||||
s32 off, struct jit_ctx *ctx, const u8 sz){
|
||||
s16 off, struct jit_ctx *ctx, const u8 sz){
|
||||
const s8 *tmp = bpf2a32[TMP_REG_1];
|
||||
const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
|
||||
s8 rm = src;
|
||||
s32 off_max;
|
||||
|
||||
if (sz == BPF_H)
|
||||
off_max = 0xff;
|
||||
else
|
||||
off_max = 0xfff;
|
||||
|
||||
if (off < 0 || off > off_max) {
|
||||
if (!is_ldst_imm(off, sz)) {
|
||||
emit_a32_mov_i(tmp[0], off, ctx);
|
||||
emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
|
||||
rm = tmp[0];
|
||||
|
|
|
@ -559,6 +559,22 @@ config ARM64_ERRATUM_1463225
|
|||
|
||||
If unsure, say Y.
|
||||
|
||||
config ARM64_ERRATUM_1542419
|
||||
bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
|
||||
default y
|
||||
help
|
||||
This option adds a workaround for ARM Neoverse-N1 erratum
|
||||
1542419.
|
||||
|
||||
Affected Neoverse-N1 cores could execute a stale instruction when
|
||||
modified by another CPU. The workaround depends on a firmware
|
||||
counterpart.
|
||||
|
||||
Workaround the issue by hiding the DIC feature from EL0. This
|
||||
forces user-space to perform cache maintenance.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config CAVIUM_ERRATUM_22375
|
||||
bool "Cavium erratum 22375, 24313"
|
||||
default y
|
||||
|
|
|
@ -72,6 +72,10 @@ stack_protector_prepare: prepare0
|
|||
include/generated/asm-offsets.h))
|
||||
endif
|
||||
|
||||
# Ensure that if the compiler supports branch protection we default it
|
||||
# off.
|
||||
KBUILD_CFLAGS += $(call cc-option,-mbranch-protection=none)
|
||||
|
||||
ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
|
||||
KBUILD_CPPFLAGS += -mbig-endian
|
||||
CHECKFLAGS += -D__AARCH64EB__
|
||||
|
|
|
@ -227,7 +227,7 @@
|
|||
|
||||
display_clocks: clock@0 {
|
||||
compatible = "allwinner,sun50i-a64-de2-clk";
|
||||
reg = <0x0 0x100000>;
|
||||
reg = <0x0 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
|
|
|
@ -77,8 +77,7 @@
|
|||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu",
|
||||
"arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
@ -71,8 +71,7 @@
|
|||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu",
|
||||
"arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
@ -2365,7 +2365,7 @@
|
|||
reg = <0x0 0xff400000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
||||
clock-names = "ddr";
|
||||
clock-names = "otg";
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "peripheral";
|
||||
|
|
|
@ -152,6 +152,10 @@
|
|||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&frddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&frddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -327,7 +327,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <60000000>;
|
||||
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
|
|
@ -363,6 +363,7 @@
|
|||
compatible = "brcm,bcm43438-bt";
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wakeup";
|
||||
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <2000000>;
|
||||
clocks = <&wifi32k>;
|
||||
|
|
|
@ -155,12 +155,12 @@
|
|||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii-txid";
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii-txid";
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
|
|
|
@ -132,12 +132,12 @@
|
|||
&fman0 {
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
|
|
|
@ -743,6 +743,7 @@
|
|||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_5v_p>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -82,7 +82,7 @@
|
|||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
gmac0: ethernet@ff800000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
reg = <0xff800000 0x2000>;
|
||||
interrupts = <0 90 4>;
|
||||
interrupt-names = "macirq";
|
||||
|
@ -97,7 +97,7 @@
|
|||
};
|
||||
|
||||
gmac1: ethernet@ff802000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
reg = <0xff802000 0x2000>;
|
||||
interrupts = <0 91 4>;
|
||||
interrupt-names = "macirq";
|
||||
|
@ -112,7 +112,7 @@
|
|||
};
|
||||
|
||||
gmac2: ethernet@ff804000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
|
||||
reg = <0xff804000 0x2000>;
|
||||
interrupts = <0 92 4>;
|
||||
interrupt-names = "macirq";
|
||||
|
|
|
@ -367,6 +367,7 @@
|
|||
pinctrl-0 = <&cp0_copper_eth_phy_reset>;
|
||||
reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <10000>;
|
||||
};
|
||||
|
||||
switch0: switch0@4 {
|
||||
|
|
|
@ -1397,8 +1397,8 @@
|
|||
"venc_lt_sel";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
|
||||
<&topckgen CLK_TOP_VENC_LT_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
|
||||
<&topckgen CLK_TOP_UNIVPLL1_D2>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
|
||||
<&topckgen CLK_TOP_VCODECPLL_370P5>;
|
||||
};
|
||||
|
||||
vencltsys: clock-controller@19000000 {
|
||||
|
|
|
@ -1151,7 +1151,7 @@
|
|||
};
|
||||
|
||||
pcie@14100000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1197,7 +1197,7 @@
|
|||
};
|
||||
|
||||
pcie@14120000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1243,7 +1243,7 @@
|
|||
};
|
||||
|
||||
pcie@14140000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1289,7 +1289,7 @@
|
|||
};
|
||||
|
||||
pcie@14160000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1335,7 +1335,7 @@
|
|||
};
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1381,7 +1381,7 @@
|
|||
};
|
||||
|
||||
pcie@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
|
@ -1430,6 +1430,105 @@
|
|||
0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
|
||||
};
|
||||
|
||||
pcie_ep@14160000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
|
||||
0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
num-lanes = <4>;
|
||||
num-ib-windows = <2>;
|
||||
num-ob-windows = <8>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_4>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
nvidia,bpmp = <&bpmp 4>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
};
|
||||
|
||||
pcie_ep@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
|
||||
0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
num-lanes = <8>;
|
||||
num-ib-windows = <2>;
|
||||
num-ob-windows = <8>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
};
|
||||
|
||||
pcie_ep@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
|
||||
0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
num-lanes = <8>;
|
||||
num-ib-windows = <2>;
|
||||
num-ob-windows = <8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
};
|
||||
|
||||
sysram@40000000 {
|
||||
compatible = "nvidia,tegra194-sysram", "mmio-sram";
|
||||
reg = <0x0 0x40000000 0x0 0x50000>;
|
||||
|
|
|
@ -1318,6 +1318,7 @@
|
|||
ipmmu_vip0: mmu@e7b00000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7b00000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
@ -1325,6 +1326,7 @@
|
|||
ipmmu_vip1: mmu@e7960000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7960000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 11>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
|
|
@ -86,13 +86,13 @@
|
|||
assigned-clock-rate = <50000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC2PHY>;
|
||||
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rk805: rk805@18 {
|
||||
rk805: pmic@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
|
|
@ -169,7 +169,7 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rk805: rk805@18 {
|
||||
rk805: pmic@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
|
|
@ -410,7 +410,7 @@
|
|||
reset-names = "usb3-otg";
|
||||
status = "disabled";
|
||||
|
||||
usbdrd_dwc3_0: dwc3 {
|
||||
usbdrd_dwc3_0: usb@fe800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe800000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
@ -446,7 +446,7 @@
|
|||
reset-names = "usb3-otg";
|
||||
status = "disabled";
|
||||
|
||||
usbdrd_dwc3_1: dwc3 {
|
||||
usbdrd_dwc3_1: usb@fe900000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe900000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
@ -1881,10 +1881,10 @@
|
|||
gpu: gpu@ff9a0000 {
|
||||
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "gpu", "job", "mmu";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
power-domains = <&power RK3399_PD_GPU>;
|
||||
status = "disabled";
|
||||
|
|
|
@ -307,6 +307,7 @@
|
|||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
||||
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
||||
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
||||
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
|
||||
|
@ -346,6 +347,7 @@
|
|||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 152 2>;
|
||||
assigned-clocks = <&k3_clks 152 2>;
|
||||
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
||||
|
||||
|
|
|
@ -30,7 +30,7 @@ static int nhpoly1305_neon_update(struct shash_desc *desc,
|
|||
return crypto_nhpoly1305_update(desc, src, srclen);
|
||||
|
||||
do {
|
||||
unsigned int n = min_t(unsigned int, srclen, PAGE_SIZE);
|
||||
unsigned int n = min_t(unsigned int, srclen, SZ_4K);
|
||||
|
||||
kernel_neon_begin();
|
||||
crypto_nhpoly1305_update_helper(desc, src, n, _nh_neon);
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue