drm/admgpu: move XDMA golden registers to dce code
Already moved other display registers. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -120,10 +120,19 @@ static const u32 golden_settings_tonga_a11[] =
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mmHDMI_CONTROL, 0x31000111, 0x00000011,
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};
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static const u32 tonga_mgcg_cgcg_init[] =
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{
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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};
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static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_TONGA:
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amdgpu_program_register_sequence(adev,
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tonga_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
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amdgpu_program_register_sequence(adev,
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golden_settings_tonga_a11,
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(const u32)ARRAY_SIZE(golden_settings_tonga_a11));
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@ -120,10 +120,19 @@ static const u32 cz_golden_settings_a11[] =
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mmFBC_MISC, 0x1f311fff, 0x14300000,
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};
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static const u32 cz_mgcg_cgcg_init[] =
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{
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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};
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static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_CARRIZO:
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amdgpu_program_register_sequence(adev,
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cz_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
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amdgpu_program_register_sequence(adev,
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cz_golden_settings_a11,
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(const u32)ARRAY_SIZE(cz_golden_settings_a11));
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@ -173,8 +173,6 @@ static const u32 tonga_mgcg_cgcg_init[] =
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mmPCIE_DATA, 0x000f0000, 0x00000000,
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mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
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mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
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mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
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};
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@ -193,8 +191,6 @@ static const u32 cz_mgcg_cgcg_init[] =
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mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
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mmPCIE_INDEX, 0xffffffff, 0x0140001c,
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mmPCIE_DATA, 0x000f0000, 0x00000000,
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mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
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mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
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mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
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mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
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};
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