ARM: Add common entry code for system with two VICs
Add a common entry-macro-vic2.S for systems where there are two VICs so that the machine or platform directories just need to setup the correct information before including <asm/entry-macro-vic2.S> into their own entry-macro.S file. Since this code is from the S3C64XX project, we update the S3C64XX machine entry code to use this new header. Signed-off-by: Ben Dooks <ben-linux@fluff.org>hifive-unleashed-5.1
Ben Dooks
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51022cf659
commit
5b39be4637
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@ -0,0 +1,57 @@
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/* arch/arm/include/asm/entry-macro-vic2.S
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*
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* Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Low-level IRQ helper macros for a device with two VICs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/* This should be included from <mach/entry-macro.S> with the necessary
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* defines for virtual addresses and IRQ bases for the two vics.
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*
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* The code needs the following defined:
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* IRQ_VIC0_BASE IRQ number of VIC0's first IRQ
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* IRQ_VIC1_BASE IRQ number of VIC1's first IRQ
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* VA_VIC0 Virtual address of VIC0
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* VA_VIC1 Virtual address of VIC1
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*
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* Note, code assumes VIC0's virtual address is an ARM immediate constant
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* away from VIC1.
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*/
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#include <asm/hardware/vic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =VA_VIC0
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ check the vic0
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mov \irqnr, #IRQ_VIC0_BASE + 31
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ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
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teq \irqstat, #0
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@ otherwise try vic1
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addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
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addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
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ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
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teqeq \irqstat, #0
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clzne \irqstat, \irqstat
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subne \irqnr, \irqnr, \irqstat
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.endm
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@ -12,33 +12,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware/vic.h>
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#include <mach/map.h>
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#include <plat/irqs.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =S3C_VA_VIC0
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ check the vic0
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mov \irqnr, # S3C_IRQ_OFFSET + 31
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ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
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teq \irqstat, #0
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@ otherwise try vic1
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addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
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addeq \irqnr, \irqnr, #32
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ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
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teqeq \irqstat, #0
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clzne \irqstat, \irqstat
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subne \irqnr, \irqnr, \irqstat
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.endm
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#include <asm/entry-macro-vic2.S>
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@ -70,8 +70,8 @@
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#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
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/* place VICs close together */
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#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
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#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
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#define VA_VIC0 (S3C_VA_IRQ + 0x00)
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#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
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/* compatibiltiy defines. */
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#define S3C_PA_TIMER S3C64XX_PA_TIMER
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@ -20,7 +20,7 @@
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*/
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static inline u32 s3c24xx_ostimer_pending(void)
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{
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u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
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u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
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return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
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}
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@ -78,12 +78,12 @@ static struct map_desc s3c_iodesc[] __initdata = {
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_VIC0,
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.virtual = (unsigned long)VA_VIC0,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_VIC1,
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.virtual = (unsigned long)VA_VIC1,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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@ -24,8 +24,8 @@
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#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
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#define S3C_VIC0_BASE S3C_IRQ(0)
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#define S3C_VIC1_BASE S3C_IRQ(32)
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#define IRQ_VIC0_BASE S3C_IRQ(0)
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#define IRQ_VIC1_BASE S3C_IRQ(32)
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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@ -59,8 +59,8 @@
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/* VIC based IRQs */
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#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
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#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
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#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
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#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
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/* VIC0 */
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@ -54,8 +54,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0);
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vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0);
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vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
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vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
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/* add the timer sub-irqs */
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