Samsung DTS changes for DMC driver for v5.5
Add bindings and update device tree sources of Exynos5422 platforms with new Dynamic Memory Controller nodes and properties. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl2t8NMQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD17muD/0a22/dCXG1vYCXSwwwUFIqojN/To6EJOBe ZEOJ6vGSabtzroL9jPvmGR1MifCrsNwckvuzaR2bh1eS9+xnISzz12/bP5omnAa+ Frdm09vulNHVR3KsXUIaHlnsenbxPbdnvPmqXx6mZEX1XaVOfRSRjwPuZUcKNpzh n48W4u/noZLZxBzN4hn4i2hcJUdjA8IirUNmxZZU4v36kIAB6hK3AUHzeTulSvDT ypHMBUIemI3qRNv/+Xi8o0JcjNoUfSCRE3rYg5gf8HQOB/0GBffA4VEq/7XPj8v7 7SZ0LBDYuL86dj6NcHKB2tpqBym0wBPJWOxBq3bNik1cnS1wk9XxwuP/YeQTMqrB XuzccIR284Wyyo1XbjLVAyQ4v33i85ZMhsiocdWNpl/lFxSjhtW3iH7KOnOZYMlQ e6PCr/ZsfS724E1dqcT0XhCQAMpW08PDoFXPkExyxc7CY8Ma7MWzxYtstflf5Aht jAWOrIKbPZnBbrxWmE+ai9GMXRFpN6y7zyW0GmesAYsyD3/J/iLPsKGdF1FVD+px i5dPffgqrrhaeQUPOPBPsqlw4dS8iqLTJVdXLHk0SDlFlVFlLRXFuU03szdUFGnr qZU7tlQdiJ37+CewT9EMsKAErkyNcSY+rNaOz8cPI9t/nqPDUIHKCZlEIKIFEuO0 giSMCuBn5A== =uqu5 -----END PGP SIGNATURE----- Merge tag 'samsung-dt-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS changes for DMC driver for v5.5 Add bindings and update device tree sources of Exynos5422 platforms with new Dynamic Memory Controller nodes and properties. * tag 'samsung-dt-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: memory-controllers: exynos5422-dmc: Correct example syntax and memory region ARM: dts: exynos: Add interrupts to DMC controller in Exynos5422 ARM: dts: exynos: Extend mapped region for DMC on Exynos5422 dt-bindings: memory-controllers: exynos5422-dmc: Add interrupt mode dt-bindings: ddr: Add bindings for Samsung LPDDR3 memories ARM: dts: exynos: Add DMC device to Exynos5422 and Odroid XU3-family boards ARM: dts: exynos: Add syscon compatible to clock controller on Exynos542x dt-bindings: memory-controllers: Add Exynos5422 DMC device description dt-bindings: ddr: Add bindings for LPDDR3 memories dt-bindings: ddr: Rename lpddr2 directory Link: https://lore.kernel.org/r/20191021180453.29455-6-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
5d8b20c131
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@ -36,7 +36,7 @@ Child nodes:
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"lpddr2-timings" provides AC timing parameters of the device for
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a given speed-bin. The user may provide the timings for as many
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speed-bins as is required. Please see Documentation/devicetree/
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bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
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bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
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Example:
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58
Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
Normal file
58
Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
Normal file
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@ -0,0 +1,58 @@
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* AC timing parameters of LPDDR3 memories for a given speed-bin.
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The structures are based on LPDDR2 and extended where needed.
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Required properties:
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- compatible : Should be "jedec,lpddr3-timings"
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- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
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- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
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Optional properties:
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The following properties represent AC timing parameters from the memory
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data-sheet of the device for a given speed-bin. All these properties are
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of type <u32> and the default unit is ps (pico seconds).
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- tRFC
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- tRRD
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- tRPab
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- tRPpb
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- tRCD
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- tRC
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- tRAS
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- tWTR
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- tWR
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- tRTP
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- tW2W-C2C
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- tR2R-C2C
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- tFAW
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- tXSR
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- tXP
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- tCKE
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- tCKESR
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- tMRD
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Example:
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timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
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compatible = "jedec,lpddr3-timings";
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reg = <800000000>; /* workaround: it shows max-freq */
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min-freq = <100000000>;
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tRFC = <65000>;
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tRRD = <6000>;
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tRPab = <12000>;
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tRPpb = <12000>;
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tRCD = <10000>;
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tRC = <33750>;
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tRAS = <23000>;
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tWTR = <3750>;
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tWR = <7500>;
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tRTP = <3750>;
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tW2W-C2C = <0>;
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tR2R-C2C = <0>;
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tFAW = <25000>;
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tXSR = <70000>;
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tXP = <3750>;
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tCKE = <3750>;
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tCKESR = <3750>;
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tMRD = <7000>;
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};
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101
Documentation/devicetree/bindings/ddr/lpddr3.txt
Normal file
101
Documentation/devicetree/bindings/ddr/lpddr3.txt
Normal file
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@ -0,0 +1,101 @@
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* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
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Required properties:
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- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
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Example "<vendor>,<type>" values:
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"samsung,K3QF2F20DB"
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- density : <u32> representing density in Mb (Mega bits)
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- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
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- #address-cells: Must be set to 1
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- #size-cells: Must be set to 0
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Optional properties:
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The following optional properties represent the minimum value of some AC
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timing parameters of the DDR device in terms of number of clock cycles.
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These values shall be obtained from the device data-sheet.
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- tRFC-min-tck
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- tRRD-min-tck
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- tRPab-min-tck
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- tRPpb-min-tck
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- tRCD-min-tck
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- tRC-min-tck
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- tRAS-min-tck
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- tWTR-min-tck
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- tWR-min-tck
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- tRTP-min-tck
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- tW2W-C2C-min-tck
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- tR2R-C2C-min-tck
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- tWL-min-tck
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- tDQSCK-min-tck
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- tRL-min-tck
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- tFAW-min-tck
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- tXSR-min-tck
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- tXP-min-tck
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- tCKE-min-tck
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- tCKESR-min-tck
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- tMRD-min-tck
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Child nodes:
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- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
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"lpddr3-timings" provides AC timing parameters of the device for
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a given speed-bin. Please see Documentation/devicetree/
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bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"
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Example:
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samsung_K3QF2F20DB: lpddr3 {
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compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
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density = <16384>;
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io-width = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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tRFC-min-tck = <17>;
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tRRD-min-tck = <2>;
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tRPab-min-tck = <2>;
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tRPpb-min-tck = <2>;
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tRCD-min-tck = <3>;
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tRC-min-tck = <6>;
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tRAS-min-tck = <5>;
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tWTR-min-tck = <2>;
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tWR-min-tck = <7>;
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tRTP-min-tck = <2>;
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tW2W-C2C-min-tck = <0>;
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tR2R-C2C-min-tck = <0>;
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tWL-min-tck = <8>;
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tDQSCK-min-tck = <5>;
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tRL-min-tck = <14>;
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tFAW-min-tck = <5>;
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tXSR-min-tck = <12>;
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tXP-min-tck = <2>;
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tCKE-min-tck = <2>;
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tCKESR-min-tck = <2>;
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tMRD-min-tck = <5>;
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timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
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compatible = "jedec,lpddr3-timings";
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/* workaround: 'reg' shows max-freq */
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reg = <800000000>;
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min-freq = <100000000>;
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tRFC = <65000>;
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tRRD = <6000>;
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tRPab = <12000>;
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tRPpb = <12000>;
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tRCD = <10000>;
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tRC = <33750>;
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tRAS = <23000>;
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tWTR = <3750>;
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tWR = <7500>;
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tRTP = <3750>;
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tW2W-C2C = <0>;
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tR2R-C2C = <0>;
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tFAW = <25000>;
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tXSR = <70000>;
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tXP = <3750>;
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tCKE = <3750>;
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tCKESR = <3750>;
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tMRD = <7000>;
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};
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}
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@ -0,0 +1,84 @@
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* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
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The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
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memory chips are connected. The driver is to monitor the controller in runtime
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and switch frequency and voltage. To monitor the usage of the controller in
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runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
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is able to measure the current load of the memory.
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When 'userspace' governor is used for the driver, an application is able to
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switch the DMC and memory frequency.
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Required properties for DMC device for Exynos5422:
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- compatible: Should be "samsung,exynos5422-dmc".
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- clocks : list of clock specifiers, must contain an entry for each
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required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
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CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
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CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
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- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
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"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
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"mout_mclk_cdrex" entries
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- devfreq-events : phandles for PPMU devices connected to this DMC.
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- vdd-supply : phandle for voltage regulator which is connected.
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- reg : registers of two CDREX controllers.
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- operating-points-v2 : phandle for OPPs described in v2 definition.
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- device-handle : phandle of the connected DRAM memory device. For more
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information please refer to documentation file:
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Documentation/devicetree/bindings/ddr/lpddr3.txt
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- devfreq-events : phandles of the PPMU events used by the controller.
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- samsung,syscon-clk : phandle of the clock register set used by the controller,
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these registers are used for enabling a 'pause' feature and are not
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exposed by clock framework but they must be used in a safe way.
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The register offsets are in the driver code and specyfic for this SoC
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type.
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Optional properties for DMC device for Exynos5422:
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- interrupt-parent : The parent interrupt controller.
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- interrupts : Contains the IRQ line numbers for the DMC internal performance
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event counters in DREX0 and DREX1 channels. Align with specification of the
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interrupt line(s) in the interrupt-parent controller.
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- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
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same as in the 'interrupts' list above.
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Example:
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ppmu_dmc0_0: ppmu@10d00000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10d00000 0x2000>;
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clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
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clock-names = "ppmu";
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events {
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ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
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event-name = "ppmu-event3-dmc0_0";
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};
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};
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};
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dmc: memory-controller@10c20000 {
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compatible = "samsung,exynos5422-dmc";
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reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
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clocks = <&clock CLK_FOUT_SPLL>,
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<&clock CLK_MOUT_SCLK_SPLL>,
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<&clock CLK_FF_DOUT_SPLL2>,
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<&clock CLK_FOUT_BPLL>,
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<&clock CLK_MOUT_BPLL>,
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<&clock CLK_SCLK_BPLL>,
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<&clock CLK_MOUT_MX_MSPLL_CCORE>,
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<&clock CLK_MOUT_MCLK_CDREX>;
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clock-names = "fout_spll",
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"mout_sclk_spll",
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"ff_dout_spll2",
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"fout_bpll",
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"mout_bpll",
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"sclk_bpll",
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"mout_mx_mspll_ccore",
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"mout_mclk_cdrex";
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operating-points-v2 = <&dmc_opp_table>;
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devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
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<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
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device-handle = <&samsung_K3QF2F20DB>;
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vdd-supply = <&buck1_reg>;
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samsung,syscon-clk = <&clock>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>, <16 1>;
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interrupt-names = "drex_0", "drex_1";
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};
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@ -175,7 +175,7 @@
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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compatible = "samsung,exynos5420-clock", "syscon";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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@ -237,6 +237,32 @@
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status = "disabled";
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};
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dmc: memory-controller@10c20000 {
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compatible = "samsung,exynos5422-dmc";
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reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
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interrupt-parent = <&combiner>;
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interrupts = <16 0>, <16 1>;
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interrupt-names = "drex_0", "drex_1";
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clocks = <&clock CLK_FOUT_SPLL>,
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<&clock CLK_MOUT_SCLK_SPLL>,
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<&clock CLK_FF_DOUT_SPLL2>,
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<&clock CLK_FOUT_BPLL>,
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<&clock CLK_MOUT_BPLL>,
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<&clock CLK_SCLK_BPLL>,
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<&clock CLK_MOUT_MX_MSPLL_CCORE>,
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<&clock CLK_MOUT_MCLK_CDREX>;
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clock-names = "fout_spll",
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"mout_sclk_spll",
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"ff_dout_spll2",
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"fout_bpll",
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"mout_bpll",
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"sclk_bpll",
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"mout_mx_mspll_ccore",
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"mout_mclk_cdrex";
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samsung,syscon-clk = <&clock>;
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status = "disabled";
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};
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nocp_mem0_0: nocp@10ca1000 {
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compatible = "samsung,exynos5420-nocp";
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reg = <0x10CA1000 0x200>;
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@ -273,6 +299,54 @@
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status = "disabled";
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};
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ppmu_dmc0_0: ppmu@10d00000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10d00000 0x2000>;
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clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
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clock-names = "ppmu";
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events {
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ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
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event-name = "ppmu-event3-dmc0_0";
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};
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};
|
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};
|
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|
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ppmu_dmc0_1: ppmu@10d10000 {
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compatible = "samsung,exynos-ppmu";
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reg = <0x10d10000 0x2000>;
|
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clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
|
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clock-names = "ppmu";
|
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events {
|
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ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
|
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event-name = "ppmu-event3-dmc0_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
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ppmu_dmc1_0: ppmu@10d60000 {
|
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compatible = "samsung,exynos-ppmu";
|
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reg = <0x10d60000 0x2000>;
|
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clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
|
||||
clock-names = "ppmu";
|
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events {
|
||||
ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
|
||||
event-name = "ppmu-event3-dmc1_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppmu_dmc1_1: ppmu@10d70000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x10d70000 0x2000>;
|
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clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
|
||||
clock-names = "ppmu";
|
||||
events {
|
||||
ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
|
||||
event-name = "ppmu-event3-dmc1_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsc_pd: power-domain@10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
|
|
|
|||
|
|
@ -34,6 +34,98 @@
|
|||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dmc_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <165000000>;
|
||||
opp-microvolt = <875000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <206000000>;
|
||||
opp-microvolt = <875000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <275000000>;
|
||||
opp-microvolt = <875000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <413000000>;
|
||||
opp-microvolt = <887500>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <543000000>;
|
||||
opp-microvolt = <937500>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <633000000>;
|
||||
opp-microvolt = <1012500>;
|
||||
};
|
||||
opp06 {
|
||||
opp-hz = /bits/ 64 <728000000>;
|
||||
opp-microvolt = <1037500>;
|
||||
};
|
||||
opp07 {
|
||||
opp-hz = /bits/ 64 <825000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
samsung_K3QF2F20DB: lpddr3 {
|
||||
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
|
||||
density = <16384>;
|
||||
io-width = <32>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tRFC-min-tck = <17>;
|
||||
tRRD-min-tck = <2>;
|
||||
tRPab-min-tck = <2>;
|
||||
tRPpb-min-tck = <2>;
|
||||
tRCD-min-tck = <3>;
|
||||
tRC-min-tck = <6>;
|
||||
tRAS-min-tck = <5>;
|
||||
tWTR-min-tck = <2>;
|
||||
tWR-min-tck = <7>;
|
||||
tRTP-min-tck = <2>;
|
||||
tW2W-C2C-min-tck = <0>;
|
||||
tR2R-C2C-min-tck = <0>;
|
||||
tWL-min-tck = <8>;
|
||||
tDQSCK-min-tck = <5>;
|
||||
tRL-min-tck = <14>;
|
||||
tFAW-min-tck = <5>;
|
||||
tXSR-min-tck = <12>;
|
||||
tXP-min-tck = <2>;
|
||||
tCKE-min-tck = <2>;
|
||||
tCKESR-min-tck = <2>;
|
||||
tMRD-min-tck = <5>;
|
||||
|
||||
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
/* workaround: 'reg' shows max-freq */
|
||||
reg = <800000000>;
|
||||
min-freq = <100000000>;
|
||||
tRFC = <65000>;
|
||||
tRRD = <6000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRCD = <10000>;
|
||||
tRC = <33750>;
|
||||
tRAS = <23000>;
|
||||
tWTR = <3750>;
|
||||
tWR = <7500>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tR2R-C2C = <0>;
|
||||
tFAW = <25000>;
|
||||
tXSR = <70000>;
|
||||
tXP = <3750>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tMRD = <7000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
|
|
@ -132,6 +224,15 @@
|
|||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&dmc {
|
||||
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
|
||||
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
|
||||
device-handle = <&samsung_K3QF2F20DB>;
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsi2c_4 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -634,6 +735,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc0_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ppmu_dmc0_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ppmu_dmc1_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ppmu_dmc1_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu_cpu0 {
|
||||
vtmu-supply = <&ldo7_reg>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
};
|
||||
|
||||
&clock {
|
||||
compatible = "samsung,exynos5800-clock";
|
||||
compatible = "samsung,exynos5800-clock", "syscon";
|
||||
};
|
||||
|
||||
&cluster_a15_opp_table {
|
||||
|
|
|
|||
Loading…
Reference in a new issue